Fuse latch having multiplexers with reduced sizes and lower power consumption

A fuse latch circuit comprising:

• a first address line for providing true address data;
• a second address line for providing complement address data;
• an input terminal for receiving a control signal varying dependent on status of a fuse;
• a multiplexer for multiplexing the first and the second address lines in response to the control signal, wherein the multiplexer has a first transistor for receiving the true address data and a second transistor for receiving the complement address data, the first and the second transistors being a single transistor type and being enabled or disabled in response to the control signal;
• and
• a dynamic decoder for eliminating a voltage drop due to the first and the second transistors in response to a multiplexed signal from the multiplexer.

A fuse latch circuit comprising:

• a first address line for providing true address data;
• a second address line for providing complement address data;
• an input terminal for receiving a control signal varying dependent on status of the fuse;
• a multiplexer for multiplexing the first and the second address lines in response to the control signal, wherein the multiplexer has a first transistor for receiving the true address data and a second transistor for receiving the complement address data, the first and the second transistors being a single transistor type and being enabled or disabled in response to the control signal;
• and
• a voltage supply unit for providing a boost voltage to the first and the second transistors.