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US 2002/0000860 A1Published application
Method and apparatus for single-ended sense amplifier and biasing
AssigneeIntel Corporation
InventorXia Dai
Life of this patent
Estimating the term…
Abstract
A method and apparatus for generating multiple locked self-timed pulsed clock signals is disclosed. Race margins are reduced over separate clock generating circuits by sharing the necessary delay circuit elements between the multiple clock generating circuits. An edge is gated with a delayed edge to form the first clock pulse. A subsequent second clock pulse is generated by gating a partially-delayed edge with the first clock pulse, which minimizes race margins and pulse evaporation.
Claims15
An apparatus, comprising:
- an input terminal to receive an edge signal;
- a first output terminal to output a first clock signal responsive to said edge signal from a first clock pulse path;
- and
- a second output terminal to output a second clock signal responsive to said edge signal and to said first clock signal from a second clock pulse path.
1 more element
A method, comprising:
- supplying an edge signal to a first clock pulse path;
- delaying said edge signal in a first set of delay elements to produce a first delayed edge signal;
- gating said edge signal with said first delayed edge signal;
- and
- supplying a first clock signal from said first clock pulse path to a second clock pulse path.
2 more elements
An apparatus, comprising:
- means for supplying an edge signal to a first clock pulse path;
- means for delaying said edge signal in a first set of delay elements to produce a first delayed edge signal;
- means for gating said edge signal with said first delayed edge signal;
- and
- means for supplying a first clock signal from said first clock pulse path to a second clock pulse path.
2 more elements
Dependencies are inferred from the claim text.