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US 2002/0000858 A1Published application
Flip-flop circuit
OwnerShih-Lien L. Luinventor
Life of this patent
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Abstract
A low power, high performance flip-flop which does not require a full feedback path in the master stage includes a master stage driven by a data input, and an inverter. A slave stage includes a pass device for isolating the slave stage and the master stage, the slave stage having a feedback path for holding a data value passed to the slave stage.
Claims31
A flip flop, comprising:
- a master stage having a pass gate and an inverter, the pass gate connected between an external data input and the inverter, the master stage driven directly by the data input;
- and
- a slave stage having a feedback path for maintaining a data input value, the slave stage isolated from the master stage on a transition of a clock signal.
A flip-flop, comprising:
- a master stage having a first transistor, a first inverter with its input connected to the first transistor, and a first half weak feedback path;
- and
- a slave stage having a second transistor, a second inverter with its input connected to the second transistor, and a second half weak feedback path.
A flip-flop, comprising:
- a master stage having pass gate and an inverter connected to the pass gate, the pass gate connectable to an external data input;
- and
- a slave stage having a second pass gate, a second inverter, and a feedback path between an output and an input of the second inverter, the feedback path for storing a previous data input value passed to the slave stage.
A flip-flop, comprising:
- a master stage having a pass gate connectable to an external data input and an inverter connected to the pass gate;
- a slave stage having a second pass gate for connecting to the master stage, and a feedback path having a strong inverter and a weak inverter.
A flip-flop, comprising:
- a master stage having a pass transistor, an inverter, and a first half feedback path between the output and input of the inverter;
- a slave stage having a pass transistor, an inverter, and a second half feedback path between the output and input of the inverter, the slave stage connectable to the master stage through the slave stage pass transistor.
A flip-flop, comprising:
- a master stage comprising:
- a master stage pass transistor connectable to a data input;
- a master stage inverter connected to the master stage pass transistor;
- and
- a half feedback path comprising a pull up transistor, the half feedback path connected between the input and output of the master stage inverter;
- and
- a slave stage connected to the master stage, comprising:
- a slave stage pass transistor connected to the output of the master stage inverter;
- a slave stage inverter connected to the slave stage pass transistor;
- a slave stage half feedback path comprising a pull up transistor, the slave stage half feedback path connected between the input and output of the slave stage inverter;
- and
- a pull down transistor connected between the input and output of the slave stage inverter;
- wherein each pull up transistor restores a logic one signal to the data, and wherein the pull down transistor restores a logic zero signal to the data in the slave stage.
10 more elements
A method, comprising:
- supplying a data input to a first network having a pass device and an inverter;
- isolating the first network from a second network until a triggering event;
- connecting the first network to the second network to pass a new data value to the second network;
- and
- holding a passed data value in the second network using a feedback path.
2 more elements
An integrated circuit, comprising:
- a first input connection for receiving a clock signal;
- a second input connection for receiving an input data signal;
- and
- a flip-flop circuit coupled to receive the clock signal and the input data signal, the flip-flop comprising:
- a master stage having a pass gate and an inverter, the pass gate connected between an external data input and the inverter, the master stage driven directly by the data input;
- and
- a slave stage having a feedback path for maintaining a data input value, the slave stage isolated from the master stage when a clock signal is in a first state, and connectable to the master stage inverter on a transition of the clock signal to a second state.
4 more elements
Dependencies are inferred from the claim text.