Delay locked loop for timing recovery and write precompensation for a read channel of a mass data storage device, or the like

A method for selecting write precompensating clock signals in a mass data storage device, comprising:

• providing a plurality of clock selection multiplexers to each receive multiple phase separated clock signals;
• providing selection signals to said clock selection multiplexers to pass a respective selected one of said multiple clock signals to a clock selection output, wherein if one clock selection multiplexer is selected to pass a particular one of said clock signals to its clock selection output, the other clock selection multiplexers are prevented from passing said particular one of said clock signals to their respective clock selection outputs.

A method for selecting write precompensating clock signals in a mass data storage device, comprising:

• providing a plurality of clock selection multiplexers to each receive multiple phase separated clock signals;
• providing selection signals to said clock selection multiplexers to pass a respective selected one of said multiple clock signals to a clock selection output, wherein if one clock selection multiplexer is selected to pass a particular one of said clock signals to its clock selection output, the other clock selection multiplexers are prevented from passing said particular one of said clock signals to their respective clock selection outputs;
• and providing a plurality of output multiplexers connected to receive outputs from said clock selection multiplexers, and controlling each of said output multiplexers to select which of said clock selection multiplexer outputs is passed as a circuit output.