Bus driver circuit
AssigneeNEC Corporation
InventorHiroshi Kamiya
Life of this patent
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Abstract
A bus driver circuit includes a plurality of first MOS transistors connected in series between a data input terminal and a data output terminal, and a plurality of second controlling MOS transistors. Sources of said plurality of first MOS transistors are connected to drains of said plurality of second controlling MOS transistors. Also, gates of said plurality of second controlling MOS transistors to control signal source means for selectively turning ON and OFF said plurality of second controlling MOS transistors. The bus driver circuit thus constructed permits selection of optimal rise-up and fall-down transition period for achieving high speed and efficient data transmission.
Claims25
A bus driver circuit comprising:
- a plurality of first MOS transistors connected in series between a data input terminal and a data output terminal, and a plurality of second controlling MOS transistors;
- sources of said plurality of first MOS transistors being connected to drains of said plurality of second controlling MOS transistors;
- and
- gates of said plurality of second controlling MOS transistors to control signal source means for selectively turning ON and OFF said plurality of second controlling MOS transistors.
A bus driver circuit comprising:
- a plurality of first NPN transistors connected in series between a data input terminal and a data output terminal, and a plurality of second controlling NPN transistors;
- sources of said plurality of first NPN transistors being connected to drains of said plurality of second controlling NPN transistors;
- and
- gates of said plurality of second controlling NPN transistors to control signal source means for selectively turning ON and OFF said plurality of second controlling NPN transistors.
A device driver circuit comprising:
- an input terminal inputting an input signal;
- a delay circuit for outputting a delayed signal generated by delaying said input signal from said input terminal for a selected one of a plurality of preset delay periods;
- an output circuit for outputting an output signal with superimposing the input signal from said input terminal and said delayed signal from said delay circuit;
- and
- an output terminal outputting the output signal from said output circuit.
A signal output device comprising:
- an output portion for outputting a signal to a bus transmission line;
- and
- a variable impedance position provided between said output portion and said bus transmission line and generates an arbitrary impedance.
A bus driver circuit comprising:
- a plurality of MOS transistors connected in series between a data input terminal and a data output terminal, a plurality of controlling MOS transistors, and a signal output circuit having an output portion for generating a signal and a variable impedance means for arbitrarily generating impedance;
- source of said plurality of MOS transistors being connected to drains of said controlling MOS transistors;
- gates of said plurality of controlling MOS transistors being connected to a control signal source for receiving a plurality of control signals respectively for selectively turning ON and OFF said plurality of controlling MOS transistors;
- and
- said data input terminal being connected to said signal output circuit.
A device driver circuit comprising:
- an input terminal for inputting an input signal;
- a delay circuit for outputting a delayed signal generated by delaying said input signal from said input terminal for a selected one of a plurality of preset delay periods;
- an output circuit for outputting an output signal with superimposing the input signal from said input terminal and said delayed signal from said delay circuit;
- an output terminal outputting the output signal from said output circuit;
- and
- a signal output circuit having an output portion for outputting a signal and a variable impedance means for arbitrarily generating an impedance, said signal output circuit being connected to said input terminal.
Dependencies are inferred from the claim text.