Input Buffer Circuit For RF Phase-Locked Loops
AssigneeSamsung Electronics Co., Ltd.
InventorSang-Oh Lee
Life of this patent
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Abstract
An input buffer circuit includes a first amplifier having low load impedance and a second amplifier having high load impedance. The output signals of the input buffer circuit have wide bandwidth, although the input buffer circuit has two stage amplifiers. In addition, the bandwidth can be controlled by resistors as an equivalent active inductance of the input buffer circuit. Further, the input buffer circuit can reduce the power consumption compared with conventional input buffer circuits, since the input buffer circuit according to the present invention uses a first switching current of the first amplifier as well as a second switching current of the second amplifier to load output signals.
Claims12
An input buffer circuit of a prescaler for pre-dividing an oscillating signal having a radio band frequency in a frequency divider of a radio frequency phase-locked loop (RF PLL), the input buffer circuit comprising:
- first switching means including cascode transistors, for receiving a first switching current from a power supply voltage source, switching the first switching current in response to the externally applied oscillating signal, and generating a first and a second switching signal by converting the first switching current into a first and a second switching voltage;
- second switching means for receiving a second switching current from the power supply voltage source and switching the second switching current, in response to the first and the second switching signal;
- loading means for generating a third and a fourth switching signal by converting both the first and the second switching currents into a third and a fourth switching voltage;
- and
- output driving means for outputting a first and a second output signal in response to the third and the fourth switching signal, respectively.
Dependencies are inferred from the claim text.