A low dielectric constant film produced from silicon compounds comprising silicon-carbon bonds

A process for depositing a low dielectric constant film, comprising the steps of:

• positioning a substrate having a patterned metal layer in a reactor;
• depositing a conformal lining layer on the patterned metal layer from process gases comprising an organo silane compound and an oxidizing gas;
• and
• depositing a gap filling layer on the lining layer.

A substrate processing system, comprising:

• a reactor comprising a reaction zone, a substrate holder for positioning a substrate in the reaction zone, and a vacuum system;
• a gas distribution system connecting the reaction zone of the vacuum chamber to supplies of an organo silane compound and an oxidizing gas;
• an RF generator capacitively coupled to the gas distribution system for generating a plasma in the reaction zone;
• a controller comprising a computer for controlling the reactor, the gas distribution system, and the RF generator;
• and
• a memory coupled to the controller, the memory comprising a computer usable medium comprising a computer readable program code for selecting a process comprising the step of reacting the organo silane compound and the oxidizing gas at conditions sufficient to deposit an oxidized organo silane film on a substrate.

A substrate processing system, comprising:

• a reactor comprising a reaction zone, a substrate holder for positioning a substrate in the reaction zone, and a vacuum system;
• a gas distribution system connecting the reaction zone of the vacuum chamber to supplies of an organo silane compound and an oxidizing gas;
• an RF generator capacitively coupled to the gas distribution system for generating a plasma in the reaction zone;
• a controller comprising a computer for controlling the reactor, the gas distribution system, and the RF generator;
• and
• a memory coupled to the controller, the memory comprising a computer usable medium comprising a computer readable program code for selecting a process comprising the steps of:
• positioning a substrate having a patterned metal layer in a reactor;
• depositing a conformal lining layer on the patterned metal layer from process gases comprising the organo silane compound and the oxidizing gas;
• and
• depositing a gap filling layer on the lining layer.

A method of forming a dual damascene structure, comprising:

• depositing a first dielectric film on a substrate;
• depositing a low k etch stop on the first dielectric film by reacting an organo silane with an oxidizing gas;
• pattern etching the low k etch stop to define a vertical interconnect opening and expose the first dielectric film;
• depositing a second dielectric film on the low k etch stop and the exposed first dielectric film;
• and
• pattern etching the second dielectric film to define a horizontal interconnect and continuing to etch the exposed first dielectric film to define the vertical interconnect.

A dual damascene structure, comprising:

• a first dielectric layer defining one or more vertical interconnects;
• a low k patterned etch stop overlying the first low k dielectric layer defining the one or more vertical interconnects, the etch stop comprising an oxidized organo silane;
• and
• a second dielectric layer overlying the patterned low k etch stop and defining one or more horizontal interconnects.

A method of forming a dual damascene structure, comprising:

• depositing a first dielectric film on a substrate;
• depositing an etch stop on the first dielectric film;
• pattern etching the etch stop to define a vertical interconnect opening and expose the first dielectric film;
• depositing a second dielectric film on the etch stop and the exposed first dielectric film by reacting an organo silane with an oxidizing gas;
• and
• pattern etching the second dielectric film to define a horizontal interconnect and continuing to etch the exposed first dielectric film to define the vertical interconnect.

A dual damascene structure, comprising:

• a first low k dielectric layer defining one or more vertical interconnects;
• a patterned etch stop overlying the first low k dielectric layer and defining the one or more vertical interconnects;
• and
• a second dielectric layer overlying the patterned etch stop and defining one or more horizontal interconnects, the second dielectric layer comprising an oxidized organo silane.

An integrated circuit structure, comprising:

• a premetal dielectric layer;
• a low k dielectric adhesive layer having a thickness from 50 to 200 Å overlying the premetal dielectric layer, the adhesive layer comprising an oxidized organo silane compound;
• and
• an intermetal dielectric layer overlying the low k dielectric adhesive layer.

A dual damascene structure, comprising:

• a dielectric layer defining one or more vertical interconnects;
• a first adhesive layer having a thickness from about 50 to about 200 Å overlying the first dielectric layer and defining the one or more vertical interconnects, the first adhesive layer comprising an oxidized organo silane film;
• a silicon oxide or silicon nitride etch stop overlying the first adhesive layer and defining the one or more vertical interconnects;
• a second adhesive layer having a thickness from about 50 to about 200 Å overlying the etch stop and defining one or more horizontal interconnects, the second adhesive layer comprising an oxidized organo silane film;
• and
• a second dielectric layer overlying the second adhesive layer and defining the one or more horizontal interconnects.