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US 2002/0000596 A1Published application
Method for improved processing and etchback of a container capacitor
AssigneeMicron Technology, Inc.
InventorRobert K. Carstensen
Life of this patent
Estimating the term…
Abstract
A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.
Claims81
An integrated circuit capacitor comprising:
- a first electrode and a second electrode formed on a substrate;
- and
- a dielectric provided between said electrodes, said capacitor having a first lower section formed in a first insulating layer and a second upper section formed in a second insulating layer, said first lower section being formed beneath said second upper section and wherein said upper section has a width greater than said lower section.
A computer system comprising:
- a processor;
- and
- a memory circuit connected to the processor, wherein at least one of said processor and memory circuit contains at least one capacitor formed on a substrate having a first electrode and a second electrode with a dielectric layer provided between said electrodes, said capacitor having a first lower section formed in a first insulating layer and a second upper section formed in a second insulating layer, said first lower section being formed beneath said second upper section and wherein said upper section has a width greater than said lower section.
A memory cell comprising:
- a transistor;
- and
- a capacitor formed on a substrate having a first electrode and a second electrode with a dielectric layer provided between said electrodes, said transistor and capacitor being connected in a memory array, said capacitor having a first lower section formed in a first insulating layer and a second upper section formed in a second insulating layer, said first lower section being formed beneath said second upper section and wherein said upper section has a width greater than said lower section.
A DRAM cell having a container capacitor, said capacitor comprising:
- a first electrode and a second electrode formed on a substrate;
- and
- a dielectric provided between said electrodes, said capacitor having a first lower section formed in a first insulating layer and a second upper section formed in a second insulating layer, said first lower section being formed beneath said second upper section and wherein said upper section has a width greater than said lower section.
A method for fabricating an integrated circuit capacitor comprising:
- forming a container opening in a first insulating layer formed over a substrate;
- forming an oxide layer over said substrate in said container opening;
- forming a plug over said oxide layer;
- forming a second insulating layer over said conductive plug and said first insulating layer;
- etching said second insulating layer such that the space formed in said second insulating layer is wider than said plug;
- removing said plug and said oxide layer to form a container opening;
- forming a first conductive layer in said container opening over an active area of said substrate;
- forming a first dielectric layer atop said first conductive layer;
- and
- forming a second conductive layer atop said dielectric layer.
7 more elements
A method for fabricating a DRAM cell container capacitor comprising:
- forming a container opening in a first insulating layer formed over a substrate;
- forming an oxide layer over said substrate;
- forming a plug over said oxide layer;
- forming a second insulating layer over said plug and said first insulating layer;
- etching said second insulating layer such that the space formed in said second insulating layer is larger than said plug;
- removing said plug and said oxide layer to form a container opening;
- forming a first conductive layer in said container opening over an active area of said substrate;
- forming a first dielectric layer atop said first conductive layer;
- and
- forming a second conductive layer atop said dielectric layer.
7 more elements
A capacitor structure formed by the method comprising:
- forming a container opening in a first insulating layer formed over a substrate;
- forming an oxide layer over said substrate;
- forming a plug over said oxide layer;
- forming a second insulating layer over said plug and said first insulating layer;
- etching said second insulating layer such that the space formed in said second insulating layer is wider than said plug;
- removing said plug and said oxide layer to form a container opening;
- forming a first conductive layer in said container opening over an active area of said substrate;
- forming a first dielectric layer atop said first conductive layer;
- and
- forming a second conductive layer atop said dielectric layer.
7 more elements
A method for fabricating an integrated circuit capacitor comprising:
- providing a first insulating layer formed over a substrate having a first opening;
- providing a second insulating layer over said first insulating layer having a second opening which has a greater width than said first opening;
- forming a first conductive layer over said container openings;
- forming a first dielectric layer atop said first conductive layer;
- and
- forming a second conductive layer atop said dielectric layer.
3 more elements
Dependencies are inferred from the claim text.