System with meshed power and signal buses on cell array

A semiconductor memory device, comprising:

• a semiconductor substrate;
• a subarray portion including a plurality of memory cells each being arranged at the intersection of bit line extending in a column direction and word line extending in a row direction;
• a fit peripheral circuit portion being adjacent to said sub-array in said row direction;
• a second peripheral circuit portion being adjacent to said sub-array in said row direction;
• a third peripheral circuit portion at the intersection of said first and second peripheral circuit portions;
• a plurality of first voltage supply lines each extending in said column direction and formed over said bit lines and word lines;
• a plurality of second voltage supply lines each extending in said row direction and formed over said bit lines and word lines, and said second voltage supply lines formed by a conductive layer which is different from that of said first voltage lines, and said second voltage lines formed over said sub-array portion and said second peripheral circuit portion;
• a third voltage supply line comprised of said first conductive layer and extending over said second and third peripheral circuit portion,
• wherein said first and second voltage supply lines are connected each other at the intersection of said first and second voltage supply lines over said sub-array portion,
• wherein said second and third voltage supply lines are connected each other at the intersection of said second and third voltage supply lines over said second peripheral circuit portion, and
• wherein said first and second voltage supply lines each has predetermined width which is larger than that of said third voltage supply line.

A semiconductor memory device including a plurality of memory cells formed on a semiconductor substrate, complementary first and second bit lines to which said memory cells are connected, a first and second MOSFET connected in series between said first and second bit lines and third MOSFET connected between said first and second bit lines, comprising:

• an active region formed on the main surface of said semiconductor substrate, in order to form said first, second and third MOSFETs;
• a first, a second and a third semiconductor region formed in said active region;
• an insulating film formed between said first, second and third semiconductor region and said first and second bit lines, said insulating film having a first through hole for connecting said first semiconductor region to said first bit line, a second through hole for connecting said second semiconductor region to said second bit line and a third through hole formed over said third semiconductor region;
• and
• a gate electrode arranged between said first and second semiconductor regions, between second and third semiconductor regions and between said third and first semiconductor regions,
• wherein said first, second and third through holes constitute a triangle, and the triangle corresponding complementary bit lines and the triangle corresponding adjacent complementary bit lines are mirror symmetrical relationship.

A semiconductor memory device, comprising:

• a first MOSFET and a second MOSFET which constitute a sense amplifier circuit, said first and second MOSFETs each having a first semiconductor region and a second semiconductor region as source and drain;
• a first memory array portion and a second memory array portion at both sides of said first and second MOSFETs;
• complementary a first and a second bit lines extending in said first memory array portion, and complementary a third and a fourth bit lines extending in said second memory array portion,
• wherein said first, second, third and fourth bit lines are comprised of a conductive layer,
• wherein said first bit line is connected to said first semiconductor region, and is connected to said third bit line via said gate electrode of said second MOSFET,
• wherein said second bit line is connected to said gate electrode of said first MOSFET and said first semiconductor region of said second MOSFET, and said second bit line is integral with said fourth bit line.

A semiconductor memory device comprising:

• a memory array having a main word line, first and second subword lines corresponding to said main word line, a plurality of data lines and a plurality of memory cells;
• a first subdecoder having an output terminal coupled to said first subword line and a first input terminal coupled to said main word line;
• a second subdecoder having an output terminal coupled to said second subword line and a first input terminal coupled to said main word line;
• a first driver, coupled to a second input terminal of said first subdecoder, outputting selection level voltage to be supplied to said first subword line;
• and
• a second driver, coupled to a second input terminal of said second subdecoder, outputting selection level voltage to be supplied to said second subword line,
• wherein said memory array is formed in a first area,
• wherein said first and second subdecoders are formed in a second area which is adjacent to said first area, and
• wherein said first and second drivers are formed in a third area which is adjacent to said second area.

A semiconductor memory device comprising:

• a memory array having a main word line, a plurality of subword lines corresponding to said main word line, a plurality of data lines and a plurality of memory cells each of which is arranged to correspond to an intersection of one of said data lines and one of said subword lines;
• a plurality of subdecoder circuits each of which includes (a) p-type first MOSFET having a drain coupled to corresponding one of said subword lines and a gate coupled to said main word line, (b) an n-type second MOSFET having a source receiving a ground potential, a drain coupled to said drain of said first MOSFET and a gate coupled to said main word line and (c) a third MOSFET having a source-drain path coupled between said drain and source of said second MOSFET;
• a plurality of signal lines each of which is coupled to a gate of corresponding said third MOSFET, wherein one of said signal lines is set to a selection level;
• and
• a plurality of drivers each of which has an input terminal coupled to corresponding one of said signal lines and an output terminal coupled to a source of corresponding said first MOSFET,
• wherein said memo array is formed in a first quadrilateral region,
• wherein said decoder circuits are formed in a second quadrilateral region which is adjacent to said first quadrilateral region, and
• wherein said drivers are formed in a third quadrilateral region which is adjacent to said second quadrilateral region.

A semiconductor device comprising:

• an array of electronic circuits;
• an electrical port located outside said array;
• a first conductor electrically connected to said electrical port and disposed over said array;
• a second conductor disposed over said array, wherein said second conductor crosses said first conductor at a cross point in said array;
• a peripheral circuit located outside of said array, wherein said peripheral circuit is electrically connected to said second conductor, and;
• means for electrically connecting said first and second conductors at said cross point,
• wherein said peripheral circuit is electrically connected to said electrical port via said first and second conductor.

A method for supplying power and signals on an array-type semiconductor device comprising:

• supplying power to a power source located outside said array;
• forming a first power bus connected to said power source and disposed over said array;
• forming a second power bus over said array, such that said second power bus crosses said first power bus at a cross point in said array;
• electrically connecting a peripheral circuit located outside of said array to said second power bus;
• and
• electrically connecting said first and second power buses at said cross point.