Chemical vapor deposition of titanium

A method for forming a titanium layer on an integrated circuit, comprising:

• forming a seed layer on the integrated circuit by combining a first precursor with a reducing agent with chemical vapor deposition (CVD);
• and
• forming the titanium layer on the integrated circuit by combining the seed layer with a second precursor with CVD;
• wherein the seed layer is formed according to the following chemical process (I):
• MRx+H2→M+alkanes, (I)
• wherein:
• M an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony;
• R is an alkyl group;
• and
• x is some integer value equal to the valence of M;
• wherein chemical process (I) is performed at a temperature greater than 400 degrees Celsius;
• and
• wherein the titanium layer is formed according to the following chemical process (II):
• TiCl4 +M→Ti+MClx, (II)
• wherein chemical process (II) is performed at a temperature greater than 400 degrees Celsius.

A method for forming a titanium layer on an integrated circuit, comprising:

• forming a seed layer on the integrated circuit by combining a first precursor with a reducing agent with chemical vapor deposition (CVD);
• forming the titanium layer on the integrated circuit by combining the seed layer with a second precursor with CVD;
• wherein the seed layer is zinc, and formed according to the following chemical process (I):
• ZnR2 +H2Zn+alkanes, (I)
• wherein R is an alkyl group and chemical process (I) is performed at a temperature greater than 400 degrees Celsius;
• and
• wherein the titanium layer is formed according to the following chemical process (II):
• TiCl4 +Zn→Ti+ZnCl2, (II)
• wherein chemical process (II) is performed at a temperature greater than 400 degrees Celsius.

A chemical vapor deposition method of providing a layer of titanium on an integrated circuit within a chemical vapor deposition (CVD) reactor, the method comprising:

• injecting a first precursor and reducing agent in the CVD reactor;
• forming a seed layer on the integrated circuit from reaction of the first precursor and the reducing agent, wherein the first precursor is an alkane;
• injecting a second precursor in the CVD reactor;
• and
• forming the titanium layer on the integrated circuit from reaction of the second precursor and the seed layer.

A chemical vapor deposition method of providing a layer of titanium on an integrated circuit within a chemical vapor deposition (CVD) reactor, the method comprising:

• injecting a first precursor and reducing agent in the CVD reactor;
• forming a seed layer on the integrated circuit from reaction of the first precursor and the reducing agent, wherein the first precursor is an alkane and wherein the alkane comprises an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony;
• injecting a second precursor in the CVD reactor;
• and
• forming the titanium layer on the integrated circuit from reaction of the second precursor and the seed layer.

A chemical vapor deposition method of providing a layer of titanium on an integrated circuit within a chemical vapor deposition (CVD) reactor, the method comprising:

• injecting a first precursor and reducing agent in the CVD reactor;
• forming zinc on the integrated circuit from a reaction of the first precursor and the first reducing agent;
• injecting a second precursor in the CVD reactor;
• and
• forming the titanium layer on the integrated circuit from a reaction of the second precursor and the zinc.

A method for forming a titanium layer supported by a substrate, comprising forming the titanium layer according to the following chemical process (III):

• TiCl4+M(source)→Ti+MClx (III)
• wherein:
• M is an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony;
• and
• x is some integer value equal to the valence of M.

A method for forming a titanium layer supported by a substrate, comprising forming the titanium layer according to the following chemical process (IV):

• MRx+H2+TiCl4→Ti+MClx+alkanes, (IV)
• wherein:
• M is an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony;
• R is an alkyl group;
• and
• x is some integer value equal to the valence of M.

A memory, comprising:

• a memory array;
• a control circuit, operatively coupled to the memory array;
• an I/O circuit, operatively coupled to the memory array;
• and
• wherein the memory array, control circuit and I/O circuit each comprise:
• a layer of a titanium alloy, wherein the titanium alloy comprises titanium and an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony;
• and
• a titanium silicide contact coupled to the layer.

A via, comprising:

• a titanium alloy layer formed overlying walls and an exposed base layer of a contact hole;
• a fill comprising a metal selected from the group consisting of tungsten and aluminum;
• and
• a titanium nitride layer interposed between the titanium alloy layer and the fill.

A via, comprising:

• a titanium alloy layer formed overlying walls and an exposed base layer of a contact hole, wherein the titanium alloy layer comprises titanium and an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony;
• a fill comprising a metal selected from the group consisting of tungsten and aluminum;
• and
• a titanium nitride layer interposed between the titanium alloy layer and the fill.

A memory device, comprising:

• a memory array;
• a control circuit operatively coupled to the memory array;
• and
• an I/O circuit operatively coupled to the memory array;
• wherein at least one of the memory array, control circuit and I/O circuit comprises a contact having a titanium alloy layer formed overlying walls of a contact hole and a titanium silicide layer formed overlying an exposed silicon base layer of the contact hole.

A memory device, comprising:

• a memory array;
• a control circuit operatively coupled to the memory array;
• and
• an I/O circuit operatively coupled to the memory array;
• wherein at least one of the memory array, control circuit and I/O circuit comprises a via having a titanium alloy layer formed overlying walls and an exposed base layer of a contact hole and a fill coupled to the titanium alloy layer, wherein the fill comprises a metal selected from the group consisting of tungsten and aluminum.

A memory device, comprising:

• memory array;
• a control circuit operatively coupled to the memory array;
• and
• an I/O circuit operatively coupled to the memory array;
• wherein at least one of the memory array, control circuit and I/O circuit comprises a titanium layer, wherein the titanium layer is produced using a method, the method comprising:
• forming a seed layer supported by a substrate by combining a first precursor with a first reducing agent;
• and
• forming the titanium layer supported by the substrate by combining a titanium-containing precursor with the seed layer.