US 2001/0056570 A1Published application

Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources

AssigneeVantis Corporation

InventorsOm P. Agrawal, Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran

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Abstract

A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.

Claims10

Dependent claims

A signal routing method for use in a field programmable gate array (FPGA) device [200] having a plurality of variable grain blocks (VGB's) [202] wherein each VGB is programmably-configurable to selectively acquire input term signals from adjacent interconnect channels [250, 260] and to produce respective result signals [f(A), fP(nT)] from the acquired signals, and further wherein each VGB is coupled to supply its result signal to a shared output component (SOC) [150] that is shared by plural VGB's, the SOC having configurable routing means [155h, v] for programmably-routing received result signals to any one or plural ones of adjacent, and differently-directed, interconnect channels [101, 102], said method comprising the steps of:

(a) configuring one or more [110, 130] of said VGB's to each supply a respective route-selection signal [DySEL, 141, 144] to a corresponding SOC [150] for causing the corresponding SOC to route a designated result signal [f(A)] to a pre-identified one or plural ones of the adjacent, and differently-directed, interconnect channels;
and
(b) configuring at least one [110, 120] of said VGB's to produce and supply said designated result signal [f(A)] to the corresponding SOC [150] so that said designated result signal can be routed to the pre-identified one or plural ones of the adjacent, and differently-directed, interconnect channels [101, 102].

Dependencies are inferred from the claim text.