Method of designing layout of semiconductor device
AssigneeFujitsu Limited
InventorMasaki Komaki
Life of this patent
Estimating the term…
Abstract
This invention provides a method and system for designing the layout of a semiconductor device that appropriately arranges various types of auxiliary cells in vacant areas. The method of the present invention is devised for laying out a plurality of auxiliary cells between logic cells in a semiconductor device. The present invention further provides an apparatus comprising a processor configured to carry out the inventive method. The apparatus of the present invention may include a cell library in which the auxiliary cells are registered and dummy cells are utilized. The present invention additionally provides a computer readable storage medium, containing a program code instructed to perform the method of the present invention.
Claims23
A method for laying out a plurality of auxiliary cells between logic cells in a semiconductor device, wherein the auxiliary cells include representative auxiliary cells and each of the auxiliary cells has a predetermined dimension, the method comprising:
- a) temporarily arranging the representative auxiliary cells in a plurality of vacant areas that are not occupied by the logic cells;
- b) obtaining a number and a total area of temporarily arranged representative auxiliary cells having the same dimension;
- and
- c) arranging a plurality of functional auxiliary cells in place of the temporarily arranged representative auxiliary cells, based on the number and the total area of the representative auxiliary cells having the same dimension and a specification of the semiconductor device, wherein each of the functional auxiliary cells has a dimension and a function that are in accordance with the dimension and a selected function of its corresponding temporarily arranged representative auxiliary cell.
An apparatus for laying out a plurality of auxiliary cells between logic cells in a semiconductor device, wherein the auxiliary cells include representative auxiliary cells and each of the auxiliary cells has a predetermined dimension, the apparatus comprising a processor for performing:
- temporarily arranging the representative auxiliary cells in a plurality of vacant areas that are not occupied by the logic cells;
- obtaining a number and a total area of temporarily arranged representative auxiliary cells having the same dimension;
- and
- arranging a plurality of functional auxiliary cells in place of the temporarily arranged representative auxiliary cells, based on the number and the total area of the representative auxiliary cells having the same dimension and a specification of the semiconductor device, wherein each of the functional auxiliary cells has a dimension and a function that are in accordance with the dimension and a selected function of its corresponding temporarily arranged representative auxiliary cell.
A computer readable storage medium for storing a program that lays out a plurality of auxiliary cells between logic cells in a semiconductor device, wherein the auxiliary cells include representative auxiliary cells and each of the auxiliary cells has a predetermined dimension, the program performing the steps of:
- temporarily arranging the representative auxiliary cells in a plurality of vacant areas that are not occupied by the logic cells;
- obtaining a number and a total area of temporarily arranged representative auxiliary cells having the same dimension;
- and
- arranging a plurality of functional auxiliary cells in place of temporarily arranged representative auxiliary cells, based on the number and the total area of the representative auxiliary cells having the same dimension and a specification of the semiconductor device, wherein each of the functional auxiliary cells has a dimension and a function that are in accordance with the dimension and a selected function of its corresponding temporarily arranged representative auxiliary cell.
A computer readable transmission medium including a program code that lays out a plurality of auxiliary cells between logic cells in a semiconductor device, wherein the auxiliary cells include representative auxiliary cells and each of the auxiliary cells has a predetermined dimension, the program code performing the steps of:
- temporarily arranging the representative auxiliary cells in a plurality of vacant areas that are not occupied by the logic cells;
- obtaining a number and a total area of temporarily arranged representative auxiliary cells having the same dimension;
- and
- arranging a plurality of functional auxiliary cells in place of the temporarily arranged representative auxiliary cells, based on the number and the total area of the representative auxiliary cells having the same dimension and a specification of the semiconductor device, wherein each of the functional auxiliary cells has a dimension and a function that are in accordance with the dimension and a selected function of its corresponding temporarily arranged representative auxiliary cell.
A method for laying out a plurality of auxiliary cells between logic cells in a semiconductor device, wherein the auxiliary cells include representative auxiliary cells and each of the auxiliary cells has a predetermined dimension, the method comprising the steps of:
- a) temporarily arranging the representative auxiliary cells largest to smallest in dimension, in a plurality of vacant areas that are not occupied by the logic cells;
- b) obtaining a number and a total area of temporarily arranged representative auxiliary cells having the same dimension;
- c) selecting a function for each of the temporarily arranged representative auxiliary cells based on the number and the total area of the representative auxiliary cells having the same dimension and a specification of the semiconductor device;
- and
- d) deleting the representative auxiliary cells;
- and
- e) arranging a plurality of functional auxiliary cells in place of the temporarily arranged representative auxiliary cells, wherein each of the functional auxiliary cells has a dimension and a function that are in accordance with the dimension and the selected function of its corresponding temporarily arranged representative auxiliary cell.
Dependencies are inferred from the claim text.