Logic compound method and logic compound apparatus
AssigneeHitachi, Ltd.
InventorsTeppei Hirotsu, Ryo Fujita, Kotaro Shimamura, Hiromichi Yamada, Dai Fujii, Haruyuki Nakayama
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Abstract
In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.
Claims12
A logical compound method, comprising the steps of:
- subdividing a logic circuit described in RTL notation into a plurality of subblocks;
- conducting logical compound for each of the subblocks;
- executing intra-subblock path delay adjustment processing in which logical compound is conducted using at least a clock definition such that delay of each intra-subblock path approaches a target value thereof for each of the subblocks;
- and
- executing inter-subblock path delay adjustment processing in which logical compound is conducted using at least a clock definition such that that delay of each path selected from a group including a path between the logic circuit and one of the subblocks and paths between the subblocks approaches a target value thereof.
A logical compound apparatus for
- subdividing a logic circuit described in RTL notation into a plurality of subblocks and for conducting logical compound for each of the subblocks, comprising;
- intra-subblock path delay adjusting means for conducting logical compound using at least a clock definition such that delay of each intra-subblock path approaches a target value thereof for each of the subblocks;
- and
- inter-subblock path delay adjusting means for conducting logical compound using at least a clock definition such that that delay of each path selected from a group including a path between the logic circuit and one of the subblocks and paths between the subblocks approaches a target value thereof.
Dependencies are inferred from the claim text.