Address parity error processing method, and apparatus and storage for the method
AssigneeFujitsu Limited
InventorYasutomo Sakurai
Life of this patent
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Abstract
To improve the processing efficiency and throughput by performing only a recovery process in read-accessing to a memory even when an address parity error has occurred in write-accessing to the memory, a selector is provided to select one of write data and a parity-bitted address for writing to the memory. If an address parity error has detected, the selector selects the parity-bitted address, in which the address parity error has occurred, instead of write data to be written to the memory during the write-accessing thereto. This address parity error processing method is particularly useful when applied to an information processor, such as a computer system, including a storage (memory)
Claims20
A method for processing an address parity error, comprising:
- (a) making a parity check over a parity-bitted address generated in write-accessing to a memory;
- and
- if said address parity error has been detected as the result of the parity check,
- (b) writing to the memory the parity-bitted address in which said address parity error has occurred.
An apparatus comprising:
- a memory for storing various kinds of data;
- an address generator for generating an address of an access destination in accessing said memory;
- a parity generator for generating at least one parity bit for the address generated by said address generator and attaching the generated parity bit to the address to obtain a parity-bitted address;
- a parity checker for making a parity check over the parity-bitted address, which is obtained by said address generator and said parity generator, in accessing to said memory;
- and
- a first selector for selecting one of write data and the parity-bitted address for writing to said memory;
- said first selector being operative, if an address parity error has been detected as the result of the parity check made by said parity checker in write-accessing to said memory, to select the parity-bitted address, in which the address parity error has occurred, for writing the selected address instead of writing the write data to said memory during the write-accessing thereto.
A storage comprising:
- a memory for storing various kinds of data;
- a parity checker for making a parity check over a parity-bitted address;
- and
- a first selector for selecting one of write data and the parity-bitted address for writing to said memory;
- said selector being operative, if an address parity error has been detected as the result of the parity check made by said parity checker in write-accessing to said memory, to select the parity-bitted address, in which the address parity error has occurred, for writing the selected address instead of writing the write data to said memory during the write-accessing thereto.
Dependencies are inferred from the claim text.