Technique for correcting single-bit errors and detecting paired double-bit errors
AssigneeSun Microsystems, Inc.
InventorRobert Cypher
Life of this patent
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AssigneeSun Microsystems, Inc.
InventorRobert Cypher
Estimating the term…
A technique to detect and correct single bit errors and to detect paired bit errors in a data block. Two bits of the data block are paired and transferred on the same data path in different cycles. Check bits are computed prior to transferring the data block. A syndrome bits vector is computed when the data block is received. The syndrome bits vector includes a number of syndrome bits that is identical to the number of check bits. A value of the syndrome bits vector is used to detect and correct single bit errors and to detect paired double bit errors that occur in the data block without using an extended check bit. If the syndrome bits vector contains all zero bits, the data block is accepted without modification. If the syndrome bits vector is identical to a predetermined special vector V, a paired double bit error has occurred and either an unrecoverable error message is generated or a re-operation on the data block is requested. If the syndrome bits vector is not identical to V but contains bits that correspond to one of a plurality of assignment vectors, a single bit error is detected and corrected. Each of the assignment vectors corresponds to one of the bits in the data block and indicates what syndrome bits the corresponding bit in the data block is contributing to.
A system for detecting and correcting errors in a data block, wherein said data block includes a plurality of bits, and wherein said plurality of bits includes data bits and check bits, said system comprising:
A system for detecting and correcting errors in a data block, wherein said data block includes a plurality of bits, wherein said plurality of bits includes data bits and check bits, said system comprising:
An apparatus for detecting and correcting errors in a data block, wherein said data block includes a plurality of bits including data bits and check bits, said apparatus comprising:
Dependencies are inferred from the claim text.