Configuration memory integrated circuit
AssigneeAltera Corporation
InventorsChris Couts-Martin, Alan Herrmann
Life of this patent
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Abstract
A configuration memory for storing information which is in-system programmable. The programming of the configuration memory may be performed using JTAG (IEEE Standard 1149.1) instructions. Furthermore, the configuration of a programmable logic device using the configuration data in the configuration memory may be initiated with a JTAG instruction. Pull-up resistors are incorporated within the configuration memory package.
Claims38
A configuration memory for use in storing information comprising:
- a memory array for storing said information;
- a data out port, said data out port being coupled with said memory array, wherein said information is transferrable out of said configuration memory through said data out port;
- a JTAG port coupled with said memory array for receiving JTAG instructions;
- and
- JTAG circuitry, said JTAG circuitry being capable of receiving one of a group of JTAG instructions from said JTAG port and controlling operation of said configuration memory according to said JTAG instruction.
A configuration memory for use in storing information comprising:
- an input/output terminal;
- a resistor, said resistor being selectively coupled between said input/output terminal and a voltage source;
- an emulation bit, said emulation bit being user programmable;
- a programmable switch, said programmable switch being coupled to said resistor, said programmable switch decoupling said resister from said input/output terminal when said emulation bit is asserted.
A configuration memory for use in storing information comprising:
- a clock signal providing a clocking event;
- a memory array for storing said information;
- first and second input control lines;
- an address counter, said address counter providing an address to said memory array, said address counter being enabled responsive to said first and second input control lines, said address counter being reset responsive to said second input control line, whereby when said address counter is enabled, said address counter is advanced to the next address in said memory array with each clocking event;
- a first output terminal;
- decode logic, said decode logic causing said first is output terminal to change from a first logic state to a second logic state when said address counter has a value corresponding to an address of a last item of information in said memory array;
- a data out port through which said information is transferrable out of said configuration memory;
- and
- JTAG circuitry, said JTAG circuitry being capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of said configuration memory according to said JTAG instruction.
A digital system comprising:
- a configuration memory, said configuration memory having a memory array for storing information, a data out port for transferring said information, and JTAG circuitry capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of said configuration memory according to said JTAG instruction;
- and
- a programmable logic device, said programmable logic device being coupled to said data out port of said configuration memory, whereby said information is transferrable from said configuration memory to said programmable logic device.
A method of configuring a programmable logic device comprising the steps of:
- providing a first configuration memory having a memory array and JTAG circuitry capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of said configuration memory according to said JTAG instruction;
- programming said memory array of said first configuration memory with configuration data;
- and
- transferring said configuration data from said memory array of said first configuration memory to said programmable logic device.
A method of programming a plurality of programmable logic devices comprising the steps of:
- providing a configuration memory having a memory array, a data out port, a JTAG port, and JTAG circuitry capable of receiving one of a group of JTAG instructions from said JTAG port and controlling operation of said configuration memory according to said JTAG instruction;
- programming said memory array of said configuration memory with configuration data;
- and
- transferring said configuration data from said configuration memory to each of said plurality of programmable logic devices.
A method of programming a configuration memory having a memory array and JTAG circuitry capable of receiving one of a group of JTAG instructions from a JTAG port and controlling operation of said configuration memory according to said JTAG instruction comprising the steps of:
- sending said JTAG instruction to said JTAG port;
- and
- transferring configuration data to said memory array of said configuration memory through said JTAG port.
Dependencies are inferred from the claim text.