Method and apparatus for fault tolerant flash upgrading
AssigneeIntel Corporation
InventorBARNES COOPER
Life of this patent
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Abstract
A novel method for upgrading a first program sequence in a computer system such that the computer system remains operable even if the upgrade process results in an incorrectly stored program sequence. The method uses the steps of storing the second program sequence in a second region of a memory, determining whether the second program sequence is stored correctly, and enabling the second program sequence if it is stored correctly. The first program sequence remains enabled if the second program sequence is not stored correctly.
Claims24
A method for upgrading a code sequence in a memory comprising the steps of:
- identifying a non-enabled region of said memory;
- and
- storing an upgrade version of said code sequence in said non-enabled region of said memory, said upgrade version of said code sequence being an upgrade of an enabled version of said code sequence in an enabled region of said memory.
A method for enabling a code sequence in a memory, said method comprising the steps of:
- determining whether a first version of said code sequence is stored successfully in a first region of said memory;
- determining whether a second version of said code sequence is stored successfully in a second region of said memory;
- enabling said first version of said code sequence, if said second version of said code sequence is not stored successfully;
- and
- enabling said second version of said code sequence, if said first version of said code sequence is not stored successfully.
A memory comprising:
- a first region having a first code sequence having a first revision identifier;
- a second region having a second code sequence having a second revision identifier, said second code sequence being an upgrade of said first code sequence;
- and
- a third region comprising a first table and a second table, wherein said first table comprises interrupt vectors pointing to a corresponding code sequence in said second table, each of said corresponding code sequences pointing to a corresponding vector of said second region.
A controller for upgrading a code sequence in a memory, said controller comprising:
- logic for identifying a non-enabled region of said memory;
- logic for storing an upgrade version of said code sequence in a non-enabled region of said memory, said upgrade version of said code sequence being an upgrade of an enabled version of said code sequence in an enabled region of said memory.
A controller for enabling a code sequence in a memory, said controller comprising:
- logic for determining whether a first code sequence having a first revision identifier is stored successfully in a first region of said memory;
- logic for determining whether a second code sequence having a second revision identifier is stored successfully in a second region of said memory;
- logic for enabling said first code sequence, if said second code sequence is not stored successfully;
- and
- logic for enabling said second code sequence, if said first code sequence is not stored successfully.
Dependencies are inferred from the claim text.