Loading patent…
AssigneeSun Microsystems, Inc.
InventorJEREMY G. HARRIS
Estimating the term…
In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the load/store unit has an error flag for marking a datum loaded to the load/store unit following a load which has completed, but resulted in an error, the processor is provided with a bit pattern generator operatively arranged in an output path from the load/store unit to at least one of the register unit and the arithmetic logic unit so that a Not-a-Number value for the invalid datum is loaded into a destination one of the floating-point registers or the arithmetic logic unit. The arithmetic logic unit is configured to propagate the Not-a-Number value as a Quiet-Not-a-Number (QNaN) value through its operations. The QNaN value may be tested for in a datum by a system software command code provided for that purpose. In other embodiments of the invention, similar functionality is provided for integer registers using poison/valid bits in conjunction with an arithmetic logic unit designed to propagate the poison/valid bits through its operations. An advantage to be gained by this design is that it becomes possible to delay testing the results of a non-faulting load, since the QNaN-like symbolic entity will propagate with the results of operations on an invalid datum, thereby keeping track of the integrity of the data.
A processor comprising a register unit having a set of registers, an arithmetic logic unit and a load/store unit, the load/store unit being connected to at least one of the register unit and the arithmetic logic unit by a data path and having an error flag for marking as invalid a datum received from an external storage element following a load which has resulted in an error, the processor further comprising a symbolic entity transmitter operatively arranged in said data path from the load/store unit so as to transmit a symbolic entity to said at least one of the register unit and the arithmetic logic unit when an invalid datum is output from the load/store unit for said at least one of the register unit and the arithmetic logic unit, the arithmetic logic unit being configured to propagate the symbolic entity, when present in an operand of an operation carried out by the arithmetic logic unit, to a result of the operation.
A method of operation of a processor comprising an instruction unit, a load/store unit, a register unit comprising a set of registers, and an arithmetic logic unit, the method comprising the steps of:
Dependencies are inferred from the claim text.