Methods of forming self-aligned contact pads using a damascene gate process

A method of forming a semiconductor device with a reduced gate resistance, the method comprising:

• forming a dummy gate pattern on a selected portion of a semiconductor substrate, the dummy gate pattern having a sidewall spacer;
• forming a first insulating layer on the semiconductor substrate, the first insulating layer having a planar top surface and having substantially the same level in height as the dummy gate pattern;
• selectively removing the dummy gate pattern with respect to the sidewall spacer and the first insulating layer to form a groove exposing the selected portion of the semiconductor substrate;
• forming a gate insulating layer on the exposed semiconductor substrate;
• partially filling the groove with a conductive material to form a gate electrode;
• and
• filling a remainder of the groove with an insulator to form a capping layer.

A method of forming a semiconductor device with a reduced gate resistance, the method comprising:

• forming a dummy gate pattern including a sacrificial insulating layer and a dummy gate material layer on a selected portion of a semiconductor substrate;
• forming a sidewall spacer on sidewall of the dummy gate pattern;
• forming a first insulating layer on an entire surface of the semiconductor substrate, the first insulating layer having substantially a planar top surface and having the same level in height as the dummy gate pattern;
• selectively removing the dummy gate pattern with respect to the sidewall spacer and the first insulating layer to form a groove exposing the selected portion of the semiconductor substrate;
• forming a gate oxide layer on the exposed semiconductor substrate;
• partially filling the groove with a low resistant conductive material to form a gate electrode;
• filling the remainder groove with an insulator having an etching selectivity with respect to the first insulating layer to form a capping layer;
• forming a second insulating layer on the first insulating layer and the capping layer, the second insulating layer having an etching selectivity with respect to the sidewall spacer and the capping layer;
• and
• selectively etching the second and first insulating layers with respect to the spacer and capping layer to form a self-aligned contact opening exposing the substrate outside of the gate electrode.

A method of forming a semiconductor device with a reduced gate resistance and a self-aligned contact pad, the method comprising:

• forming a first dummy gate pattern and a second dummy gate pattern on a semiconductor substrate, each dummy gate pattern having a sidewall spacer, the second dummy gate pattern relatively being wider than the first dummy gate pattern;
• forming a first insulating layer on an entire surface of the semiconductor substrate, the first insulating layer having a planar top surface and having the same level in height as the dummy gate patterns;
• removing the first and second dummy gate patterns to form a first and a second grooves exposing the substrate;
• forming a first and a second gate oxide layers on the first and the second grooves respectively;
• forming a low resistance material layer on the first insulating layer thereby completely filling the first groove and partially filling the second groove due to width difference therebetween;
• forming an etching stopper on the conductive material to completely fill the remainder second groove;
• etching the etching stopper until the conductive material outside of the grooves is exposed;
• using remainder etching stopper as an etch mask and etching the conductive material layer in the first groove to recess from a top surface of the first insulating layer;
• and
• forming an insulator to fill remainder first and second grooves to form a first capping layer and a second capping layer.