Clock recovery circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorKoji Okamoto
Life of this patent
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Abstract
A cross detection part detects a zero-crossing point of a reproduction signal digitalized and a phase error estimation part uses the zero-crossing point of the reproduction signal for estimating a phase error thereof. At this time, a pattern detection part detects whether a variation pattern of the reproduction signal is a specified pattern (for example, a 3T pattern for the case of DVD disks) and controls a selection part to ensure that no phase error estimation value of low reliability is utilized for controlling of a PLL for clock recovery.
Claims4
A clock recovery circuit for recovery of a clock from an input signal digitalized, said clock being in synchronization with said input signal,
- said clock recovery circuit comprising:
- a clock generation part for generating a clock signal;
- a phase error detection part for detecting a phase error of said input signal with respect to said clock signal;
- and
- a control part for controlling, based on an output of said phase error detection part, an oscillation frequency of said clock generation part so that said phase error becomes zero;
- said phase error detection part including:
- a cross detection part for generating a timing signal representative of a point at which said input signal crosses a preset value;
- a phase error estimation part for estimating, based on said timing signal, said phase error of said input signal with respect to said clock signal;
- a pattern detection part for detecting a variation pattern of said input signal;
- and
- a selection part for selecting, according to said detected variation pattern, whether said estimated phase error is output to said control part.
Dependencies are inferred from the claim text.