Semiconductor memory that enables high speed operation
AssigneeNEC Corporation
InventorsYoshinori Matsui, Hiroyuki Yamakoshi
Life of this patent
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Abstract
A semiconductor memory includes a block selection circuit, a redundancy main word decoder, a word reset circuit, and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The redundancy main word decoder generates a redundancy main word signal in response to the block selection signal. The word reset circuit outputs a word reset signal in response to the redundancy main word signal. The word driver circuit drives one of word lines in response to the word reset signal, a main word signal indicating selection of the word driver circuit, and a word decode signal indicating selection of the one of word lines.
Claims28
A semiconductor memory comprising:
- a block selection circuit outputting a block selection signal based on an address signal;
- a redundancy main word decoder generating a redundancy main word signal in response to said block selection signal;
- a word reset circuit outputting a word reset signal in response to said redundancy main word signal;
- and
- a word driver circuit which drives one of word lines in response to said word reset signal, a main word signal indicating selection of said word driver circuit, and a word decode signal indicating selection of said one of word lines.
A semiconductor memory comprising:
- a block selection circuit outputting a block selection signal based on an address signal;
- a main word decoder generating a main word signal based on said address signal and said block selection signal;
- a word reset circuit outputting a word reset signal in response to said main word signal;
- and
- a word driver circuit which drives one of word lines in response to said word reset signal, said main word signal and a word decode signal.
A method of driving a word line, comprising the steps of:
- (a) activating a block selection signal based on an address signal;
- (b) activating a redundancy main word signal in response to said block selection signal;
- (c) activating a word reset signal in response to said redundancy main word signal;
- and
- (d) activating a word line base on said word reset signal, a main word signal, and a word decode signal.
Dependencies are inferred from the claim text.