Filter characteristic regulating apparatus and regulating method therefor

A method of regulating filter characteristics for regulating a characteristic frequency of a filter device capable of regulating the characteristic frequency thereof, comprising the steps of:

• preparing a measuring signal having a known cycle of a response waveform when inputted to said filter device having a desired characteristic frequency;
• inputting said measuring signal to said filter device when said filter device is not used, and measuring the cycle of the response waveform;
• and
• comparing the cycle so measured with said known cycle and regulating the characteristic frequency of said filter device to said desired value on the basis of the comparison result.

A semiconductor amplification circuit comprising:

• a pair of differential input terminals;
• a first MOS transistor having a gate thereof connected to a mutual conductance controlling terminal;
• a pair of second and third MOS transistors having the gates thereof connected to said differential input terminals and sources thereof connected to either one of the source and drain of said first MOS transistor;
• a pair of fourth and fifth MOS transistors having the gates thereof connected to a constant bias signal input terminal and the sources thereof connected to the drains of said second and third MOS transistors, respectively;
• first and second current sources connected to the source and drain of said first MOS transistor, respectively;
• third and fourth current sources connected to the drains of said fourth and fifth MOS transistors, respectively;
• a pair of differential output terminals disposed between the drains of said fourth and fifth MOS transistors and said third and fourth current sources;
• and
• first and second capacitances having one of the ends thereof connected to the sources of said fourth and fifth MOS transistors and the other end thereof connected to a fixed potential.

An integrator comprising a semiconductor amplification circuit and a load capacitance connected to differential output terminals of said semiconductor amplification circuit, said semiconductor amplification circuit comprising:

• a pair of differential input terminals;
• a first MOS transistor having a gate thereof connected to a mutual conductance controlling terminal;
• a pair of second and third MOS transistors having the gates thereof connected to said differential input terminals and the sources thereof connected to either one of the source and drain of said first MOS transistor;
• a pair of fourth and fifth MOS transistors having the gates thereof connected to a constant bias signal input terminal and the sources thereof connected to the drains of said second and third MOS transistors, respectively;
• first and second current sources connected to the source and drain of said first MOS transistor, respectively;
• third and fourth current sources connected to the drains of said fourth and fifth MOS transistors, respectively;
• a pair of differential output terminals disposed between the drains of said fourth and fifth MOS transistors and said third and fourth current sources, respectively;
• and
• first and second capacitances having one of the ends thereof connected to the sources of said fourth and fifth MOS transistors and the other end thereof connected to a fixed potential.