Delay locked loop circuit capable of adjusting phase of clock with high precision

A delay locked loop circuit comprising:

• a phase comparator comparing a phase of a delay clock with a phase of a reference clock;
• a counter referring to a result received from said phase comparator comparing the phase of said delay clock with the phase of said reference clock, to provide a counting up/down operation and output first and second addresses;
• a first delay circuit generating in response to said reference clock first and second signals having therebetween a phase difference of a fixed amount, and responding to the generated first and second signals and referring to said first address to generate a fine adjustment clock having a phase existing between a phase of said first signal and a phase of said second signal;
• and
• a second delay circuit referring to said second address to delay said fine adjustment clock by said fixed amount multiplied by an integer to output said delay clock.