Logic circuit and its forming method

A logic circuit including:

• 127th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 127th node;
• 127th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 127th node;
• 128th n-channel field-effect transistor in which the gate is controlled by 127th node and a source drain path is connected to 128th node;
• 129th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second input signal and 128th node;
• 130th p-channel field-effect transistor in which the gate is controlled by 128th node and a source drain path is connected between first operation potential point and 130th node;
• 130th n-channel field-effect transistor in which the gate is controlled by 128th node and a source drain path is connected between second operation potential point and 130th node;
• 125th n-channel field-effect transistor in which the gate is controlled by 121st node and a source drain path is connected between third input signal and 125th node;
• and
• 126th n-channel field-effect transistor in which the gate is controlled by 130th node and a source drain path is connected between 124th node controlled by first input signal, and 125th node.

A logic circuit including:

• 120th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 120th node;
• 120th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 120th node;
• 123rd n-channel field-effect transistor in which the gate is controlled by 120th node and a source drain path is connected to fifth input signal and 124th node;
• 124th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between fourth input signal and 124th node;
• 121st p-channel field-effect transistor in which the gate is controlled by 130th node and a source drain path is connected between first operation potential point and 121st node;
• 121st n-channel field-effect transistor in which the gate is controlled by 130th node and a source drain path is connected between second operation potential point and 121st node;
• 125th n-channel field-effect transistor in which the gate is controlled by 121st node and a source drain path is connected between third input signal and 125th node;
• 126th n-channel field-effect transistor in which the gate is controlled by 130th node and a source drain path is connected between 124th node and 125th node;
• 127th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 127th node;
• 127th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 127th node;
• 128th n-channel field-effect transistor in which the gate is controlled by 127th node and a source drain path is connected between first or second operation potential point and 128th node;
• 129th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second input signal and 128th node;
• 130th p-channel field-effect transistor in which the gate is controlled by 128th node and a source drain path is connected between first operation potential point and 130th node;
• 130th n-channel field-effect transistor in which the gate is controlled by 128th node and a source drain path is connected between second operation potential point and 130th node;
• 122nd p-channel field-effect transistor in which the gate is controlled by 125th node and a source drain path is connected between first operation potential point and first output signal;
• and 122nd n-channel field-effect transistor in which the gate is controlled by 125th node and a source drain path is connected between second operation potential point and first output signal.

A logic circuit including:

• 140th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 140th node;
• 140th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 140th node;
• 143rd n-channel field-effect transistor in which the gate is controlled by 140th node and a source drain path is connected to fourth input signal and 144th node;
• 144th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between fifth input signal and 144th node;
• 141st p-channel field-effect transistor in which the gate is controlled by 150th node and a source drain path is connected between first operation potential point and 141st node;
• 141st n-channel field-effect transistor in which the gate is controlled by 150th node and a source drain path is connected between second operation potential point and 141st node;
• 145th n-channel field-effect transistor in which the gate is controlled by 141st node and a source drain path is connected between third input signal and 145th node;
• 146th n-channel field-effect transistor in which the gate is controlled by 150th node and a source drain path is connected between 144th node and 145th node;
• 147th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 147th node;
• 147th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 147th node;
• 148th n-channel field-effect transistor in which the gate is controlled by 147th node and a source drain path is connected between second input signal and 148th node;
• 149th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first or second operation potential point and 148th node;
• 150th p-channel field-effect transistor in which the gate is controlled by 148th node and a source drain path is connected between first operation potential point and 150th node;
• 150th n-channel field-effect transistor in which the gate is controlled by 148th node and a source drain path is connected between second operation potential point and 150th node;
• 142nd p-channel field-effect transistor in which the gate is controlled by 145th node and a source drain path is connected between first operation potential point and first output signal;
• 142nd n-channel field-effect transistor in which the gate is controlled by 145th node and a source drain path is connected between second operation potential point and first output signal.

A logic circuit including:

• 160th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 160th node;
• 160th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 160th node;
• 163rd n-channel field-effect transistor in which the gate is controlled by 160th node and a source drain path is connected between fifth input signal and 163rd node;
• 164th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between fourth input signal and 163rd node;
• 161st p-channel field-effect transistor in which the gate is controlled by 168th node and a source drain path is connected between first operation potential point and 161st node;
• 161st n-channel field-effect transistor in which the gate is controlled by 168th node and a source drain path is connected between second operation potential point and 161st node;
• 165th n-channel field-effect transistor in which the gate is controlled by 161st node and a source drain path is connected between third input signal and 165th node;
• 166th n-channel field-effect transistor in which the gate is controlled by 168th node and a source drain path is connected between 163rd node and 165th node;
• 167th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 168th node;
• 168th p-channel field-effect transistor in which the gate is controlled by second input signal and a source drain path is connected between first operation potential point and 168th node;
• 167th n-channel field-effect transistor in which the gate is controlled by second input signal and a source drain path is connected between 168th node and 167th node;
• 168th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 167th node;
• 162nd p-channel field-effect transistor in which the gate is controlled by 165th node and a source drain path is connected between first operation potential point and first output signal;
• and 162nd n-channel field-effect transistor in which the gate is controlled by 165th node and a source drain path is connected between second operation potential point and first output signal.

A logic circuit including:

• 184th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 185th node;
• 185th p-channel field-effect transistor in which the gate is controlled by second input signal and a source drain path is connected between first operation potential point and 185th node;
• 184th n-channel field-effect transistor in which the gate is controlled by second input signal and a source drain path is connected between 185th node and 184th node;
• 185th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 184th node;
• 180th p-channel field-effect transistor in which the gate is controlled by 185th node and a source drain path is connected between first operation potential point and 180th node;
• 180th n-channel field-effect transistor in which the gate is controlled by 185th node and a source drain path is connected between second operation potential point and 180th node;
• 182nd n-channel field-effect transistor in which the gate is controlled by 180th node and a source drain path is connected between third input signal and 182nd node;
• 183rd n-channel field-effect transistor in which the gate is controlled by 185th node and a source drain path is connected between first input signal and 182nd node;
• 181st p-channel field-effect transistor in which the gate is controlled by 182nd node and a source drain path is connected between first operation potential point and first output signal;
• and 181st n-channel field-effect transistor in which the gate is controlled by 182nd node and a source drain path is connected between second operation potential point and first output signal.

A logic circuit including:

• 120th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 120th node;
• 120th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 120th node;
• 123rd n-channel field-effect transistor in which the gate is controlled by 120th node and a source drain path is connected between fifth input signal and 124th node;
• 124th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between fourth input signal and 124th node;
• 121st p-channel field-effect transistor in which the gate is controlled by 130th node and a source drain path is connected between first operation potential point and 121st node;
• 121st n-channel field-effect transistor in which the gate is controlled by 130th node and a source drain path is connected between second operation potential point and 121st node;
• 125th n-channel field-effect transistor in which the gate is controlled by 121st node and a source drain path is connected between third input signal and 125th node;
• 126th n-channel field-effect transistor in which the gate is controlled by 130th node and a source drain path is connected between 124th node and 125th node;
• 127th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 127th node;
• 127th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 127th node;
• 128th n-channel field-effect transistor in which the gate is controlled by 127th node and a source drain path is connected between first or second operation potential point and 128th node;
• and 129th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second input signal and 128th node.

A logic circuit including:

• 140th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 140th node;
• 140th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 140th node;
• 143rd n-channel field-effect transistor in which the gate is controlled by 140th node and a source drain path is connected between fourth input signal and 144th node;
• 144th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between fifth input signal and 144th node;
• 141st p-channel field-effect transistor in which the gate is controlled by 150th node and a source drain path is connected between first operation potential point and 141st node;
• 141st n-channel field-effect transistor in which the gate is controlled by 150th node and a source drain path is connected between second operation potential point and 141st node;
• 145th n-channel field-effect transistor in which the gate is controlled by 141st node and a source drain path is connected between third input signal and 145th node;
• 146th n-channel field-effect transistor in which the gate is controlled by 150th node and a source drain path is connected between 144th node and 145th node;
• 147th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 147th node;
• 147th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 147th node;
• 148th n-channel field-effect transistor in which the gate is controlled by 147th node and a source drain path is connected between second input signal and 148th node;
• and 149th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first or second operation potential point and 148th node.

A logic circuit including:

• 160th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 160th node;
• 160th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 160th node;
• 163rd n-channel field-effect transistor in which the gate is controlled by 160th node and a source drain path is connected between fifth input signal and 163rd node;
• 164th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between fourth input signal and 163rd node;
• 161st p-channel field-effect transistor in which the gate is controlled by 168th node and a source drain path is connected between first operation potential point and 161st node;
• 161st n-channel field-effect transistor in which the gate is controlled by 168th node and a source drain path is connected between second operation potential point and 161st node;
• 165th n-channel field-effect transistor in which the gate is controlled by 161st node and a source drain path is connected between third input signal and 165th node;
• 166th n-channel field-effect transistor in which the gate is controlled by 168th node and a source drain path is connected between 163rd node and 165th node;
• and
• 167th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 168th node;
• 168th p-channel field-effect transistor in which the gate is controlled by second input signal and a source drain path is connected between first operation potential point and 168th node;
• 167th n-channel field-effect transistor in which the gate is controlled by second input signal and a source drain path is connected between 168th node and 167th node;
• and 168th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 167th node.

A logic circuit including:

• 184th p-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between first operation potential point and 185th node;
• 185th p-channel field-effect transistor in which the gate is controlled by second input signal and a source drain path is connected between first operation potential point and 185th node;
• 184th n-channel field-effect transistor in which the gate is controlled by second input signal and a source drain path is connected between 185th node and 184th node;
• 185th n-channel field-effect transistor in which the gate is controlled by first input signal and a source drain path is connected between second operation potential point and 184th node;
• 180th p-channel field-effect transistor in which the gate is controlled by 185th node and a source drain path is connected between first operation potential point and 180th node;
• and 180th n-channel field-effect transistor in which the gate is controlled by 185th node and a source drain path is connected between second operation potential point and 180th node.