Semiconductor integrated circuit and design method and manufacturing method of the same
AssigneeHitachi, Ltd.
InventorsMasayuki Sato, Kunio Uchiyama
Life of this patent
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Abstract
A conventional system for testing a semiconductor integrated circuit has a problem in that the time required to test it is long, the cost required for its test increases, and yields are reduced due to the occurrence of a failure in a test circuit itself. A plurality of programmable logic cells (LCL) having storage elements (MC1 through MC4) and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in each storage element are spread over areas other than circuit blocks (CPU, ROM, etc.) on a semiconductor chip without space. Each in-chip circuit block is tested by use of the programmable logic cell.
Claims11
A semiconductor integrated circuit comprising:
- a plurality of programmable logic cells having storage elements and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in said each storage element,
- wherein said plurality of programmable logic cells are provided in areas other than circuit blocks on a semiconductor chip.
A semiconductor integrated circuit comprising:
- a first programmable logic unit and a second programmable logic unit which are provided so as to interpose circuit blocks placed on a semiconductor chip therebetween and which respectively comprise a plurality of programmable logic cells having storage elements and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in said each storage element,
- wherein said first programmable logic unit and said second programmable logic unit are capable of accessing in parallel.
A method of designing a semiconductor integrated circuit, comprising the steps of:
- laying out a plurality of programmable logic cells having storage elements and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in said each storage element so as to spread over the entire semiconductor chip;
- thereafter determining the layout of each of circuit blocks each having a desired function;
- and
- laying out each of said circuit blocks in a layout-determined area on the chip with replacement by said programmable logic cell.
A method of manufacturing a semiconductor integrated circuit, comprising the steps of:
- laying out a plurality of programmable logic cells having storage elements and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in said each storage element so as to spread over the entire semiconductor chip;
- thereafter determining the layout of each of circuit blocks each having a desired function;
- laying out each of said circuit blocks in a layout-determined area on the chip with replacement by said programmable logic cell to thereby form the semiconductor integrated circuit;
- thereafter forming a test circuit for examining said programmable logic cells and checking at least one of said circuit blocks through the use of the programmable logic cell judged to be normal;
- and
- examining said each circuit block by said test circuit to thereby remove a defective product.
Dependencies are inferred from the claim text.