Method and system for high performance implementation of microprocessors
AssigneeRicoh Company, Ltd.
InventorSHINICHI YAMAURA
Life of this patent
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Abstract
The present invention is related to branch instructions in a pipeline process of a microprocessor system. The microprocessor system executes branch prediction if a conditional branch instruction code calls for branch prediction, and on the other hand, suspends successive instruction execution until a branch evaluation of the conditional branch instruction settles if the conditional branch instruction code does not call for branch prediction.
Claims16
A method for branch instructions in a pipeline process of a microprocessor system, comprising the steps of:
- determining whether a conditional branch instruction code should correspond to a branch prediction;
- and
- executing the branch prediction if said conditional branch instruction code corresponds the branch prediction.
A method for branch instructions in a pipeline process of a microprocessor system, comprising the steps of:
- determining whether a conditional branch instruction code should correspond to a branch prediction according to a prescribed bit in the conditional branch instruction code, which corresponds the branch prediction;
- and
- executing the branch prediction if said prescribed bit corresponds to the branch prediction.
A microprocessor executing branch instructions in a pipeline process, comprising:
- an identifier means for identifying whether a conditional branch instruction code should correspond to a branch prediction based upon a branch prediction effective bit in the conditional branch instruction code.
A microprocessor system for branch instructions in a pipeline process, comprising:
- a branch prediction unit configured to detect a prescribed bit corresponding to effective branch prediction code in a conditional branch instruction code and to determine whether said conditional branch instruction code should correspond to a branch prediction code according to said prescribed bit corresponding to the effective branch prediction code;
- and
- a branch prediction controller coupled to said branch prediction unit and configured to execute the branch prediction if said conditional branch instruction code corresponds to the branch prediction.
A microprocessor system for branch instructions in a pipeline process, comprising:
- a memory unit;
- a fetch unit that receives data from said memory unit and generates addresses based upon a program counter wherein said fetch unit is equipped with a branch prediction unit which predicts target addresses according to a condition branch instruction;
- an instruction decoder configured to decode data from the fetch unit;
- a branch prediction unit coupled to said instruction decoder and configured to execute an evaluation of a branch instruction after receiving conditional branch instruction from the instruction decoder;
- an arithmetic logic unit coupled to said instruction decoder and configured to calculate a logical computation according to the decoded data from the instruction decoder;
- and
- a reorder buffer that receives data computed by said arithmetic logic unit, and branch instruction data whether the branch prediction is taken or not taken.
Dependencies are inferred from the claim text.