Method for switching between modes of operation

A memory circuit comprising:

• control logic for providing a selected mode control signal;
• selection and temporary storage circuitry for receiving and storing a first external address;
• and
• a multiplexer coupled to the selection and temporary storage circuitry and to the control logic for receiving the first external address and the selected mode control signal respectively therefrom and for switching between a burst mode and a pipelined mode.

A method for accessing a storage device, the method comprising steps of:

• receiving a first address to the storage device;
• selecting between a burst and a pipelined mode of operation of the storage device;
• selecting between outputting information from and inputting information to the storage device;
• obtaining a second address to the storage device;
• and
• accessing a storage element of the storage device using the first address and the second address;
• the storage device being asynchronously-accessible in either of the burst mode and the pipelined mode.

A method for accessing a random access memory comprising steps of:

• receiving an external row address to the memory;
• selecting between a burst mode and a pipelined mode of operation;
• selecting between a read and a write operation;
• and
• obtaining a first external column address for accessing the memory.

A memory integrated circuit comprising:

• a memory;
• a plurality of input/output pins for providing information to and from the memory;
• a plurality of address pins for providing addresses to the memory for providing the information to and from the memory;
• and
• a mode select pin for switching as between a burst mode and a pipelined mode of operation of the memory integrated circuit.

Method for accessing several different locations in an asynchronously-accessible memory device, the method comprising steps of:

• selecting a first mode of operation;
• providing a new external address for every access associated with asynchronously accessing the device while in the first mode of operation;
• switching modes to a second mode of operation;
• providing an initial external address associated with asynchronously accessing the device in the second mode of operation;
• and
• generating at least one subsequent internal address patterned after the initial external address while in the second mode of operation.

A system comprising:

• a microprocessor;
• a memory, coupled to the microprocessor, for operating in burst or pipelined modes;
• and
• a system clock coupled to the microprocessor, the memory not operating directly off the system clock.

Method for switching between modes of operation, the method comprising steps of:

• maintaining a first enabling signal in an active state;
• maintaining a mode select signal to select a first mode;
• receiving an initial external address;
• cycling a second enabling signal from inactive to active and so forth;
• generating an internal address on a cycle of the second enabling signal base on the initial external address;
• changing the mode select signal to select a second mode while maintaining the first enabling signal in the active state, and
• receiving an external address on each cycle of the second enabling signal.

Method for switching between modes of operation, the method comprising steps of:

• maintaining a first enabling signal in an active state;
• maintaining a mode select signal to select a first mode;
• receiving a stream of addresses and cycling a second enabling signal for processing the stream of addresses;
• and
• changing the mode select signal to select a second mode.