CPU system with high-speed peripheral LSI circuit
AssigneeNEC Corporation
InventorEiji Muramatsu
Life of this patent
Estimating the term…
Abstract
A CPU system employs a general-purpose peripheral LSI circuit and a high-speed memory for the peripheral LSI circuit. A selector determines whether access from a CPU is directed to an internal circuit of the peripheral LSI circuit or an SDRAM. If the access is directed to the SDRAM, the selector stores a bus signal in a timing adjusting circuit and then reads the stored bus signal at a rate that is at least twice the rate at which the bus signal has been stored. An SDRAM interface accesses the SDRAM with the read bus signal. The internal circuit accesses the SDRAM while bus arbitration is being carried out between the internal circuit and the SDRAM interface.
Claims6
A CPU system comprising:
- a CPU;
- a peripheral LSI circuit having a first interface connected to an SDRAM interface of said CPU and a second interface for accessing an external circuit, for determining whether access from said CPU via said first interface is directed to an internal circuit of the peripheral LSI circuit or the external circuit, storing a first bus signal from said first interface if the access from said CPU is directed to the external circuit, adjusting the timing of the stored first bus signal and reading the first bus signal to generate a second bus signal having a rate which is at least twice the rate of said first bus signal, and accessing the external circuit from said second interface with said second bus signal;
- and
- an SDRAM, serving as said external circuit, connected to said second interface and accessible by said second bus signal.
A peripheral LSI circuit connectable to a CPU for realizing predetermined functions, comprising:
- an internal circuit for realizing the predetermined functions;
- a selector for determining whether access from said CPU is directed to said internal circuit or an external circuit, reading data from or writing data in said internal circuit if the access from said CPU is directed to said internal circuit, and sending a bus signal from said CPU as a first bus signal if the access from said CPU is directed to said external circuit;
- a timing adjusting circuit for storing said first bus signal and reading the stored first bus signal with predetermined timing to generate and send a second bus signal having a rate which is at least twice the rate of said first bus signal;
- and
- an SDRAM interface for accessing an SDRAM connected as said external circuit with said second bus signal from said timing adjusting circuit.
Dependencies are inferred from the claim text.