Semiconductor device and manufacture thereof

A method of fabricating a memory device, comprising the steps of:

• forming a first active region on a substrate, the first active region having a first contact section with a width not more than substantially that of an adjacent section of the first active region;
• forming a second active region on the substrate, the second active region having a second contact section with a width not more than substantially that of an adjacent section of the second active region;
• forming a first insulation layer outwardly of the first and second active regions and the substrate;
• forming an upper conductive element outwardly of the first insulation layer, the upper conductive element having an upper contact section with a width not more than substantially that of an adjacent section of the upper conductive element;
• forming a second insulation layer outwardly of the first insulation layer and the upper conductive element;
• forming a first contact hole in the first and second insulation layers exposing a first contact area of the first contact section and a first upper contact area of the upper contact section;
• forming a second contact hole in the first and second insulation layers exposing a second contact area of the second contact section and a second upper contact area of the upper contact section;
• forming a first interconnect in the first contact hole connecting the first contact area of the first active region and the first upper contact area of the upper conductive element, the first interconnect having a substantially uniform width between the first active region and the upper conductive element;
• and
• forming a second interconnect in the second contact hole connecting the second contact area of the second active region and the second upper contact area of the upper conductive element, the second interconnect having a substantially uniform width between the second active region and the upper conductive element.

An integrated circuit, comprising:

• a first conductive element having a first contact section with a width not more than substantially that of an adjacent section of the first conductive element;
• a second conductive element having a second contact section with a width not more than substantially that of an adjacent section of the second conductive element;
• an insulation layer disposed between the first and second conductive elements;
• and
• an interconnect connecting the contact sections of the first and second conductive elements, the interconnect having a substantially uniform width between the first and second conductive elements.