Method for fabricating thin film transistor
AssigneeHannstar Display Corp.
InventorsChih-Chang Chen, Jerry Ji-Ho Kung
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Abstract
A method for fabricating a thin film transistor (TFT) is provided. The method includes steps of a) providing an insulation substrate, b) forming a conductive layer on the insulation substrate, c) defining the conductive layer as a gate conducting structure by a first photolithography and etch process, d) forming a gate insulation layer, a channel layer, a junction layer, a source/drain layer and a data line layer in sequence, and etching the data line layer, the source/drain layer and the junction layer by a second photolithography and etch process to form a source/drain structure and a data line structure, and e) heat-treating the junction layer to reduce resistance between the source/drain structure and the channel layer.
Claims20
A method for fabricating a thin film transistor (TFT), comprising steps of:
- a) providing an insulation substrate;
- b) forming a conductive layer on said insulation substrate;
- c) defining said conductive layer as a gate conducting structure by a first photolithography and etch process;
- d) forming a gate insulation layer, a channel layer, a junction layer, a source/drain layer and a data line layer in sequence, and etching said data line layer, said source/drain layer and said junction layer by a second photolithography and etch process to form a source/drain structure and a data line structure;
- and
- e) heat-treating said junction layer to reduce resistance between said source/drain structure and said channel layer.
A method for fabricating a thin film transistor-liquid crystal display (TFT-LCD), comprising steps of:
- a) providing an insulation substrate;
- b) forming a conductive layer on said insulation substrate;
- c) defining said conductive layer as a gate conducting structure by a first photolithography and etch process;
- d) forming a gate insulation layer, a channel layer, a junction layer, a source/drain layer and a data line layer in sequence, and etching said data line layer, said source/drain layer and said junction layer by a second photolithography and etch process to form a source/drain structure and a data line structure;
- e) forming a passivation and defining a contact window on said passivation by a third photolithography and etch process;
- f) forming a transparent electrode layer and defining a transparent pixel electrode region by a fourth photolithography and etch process;
- and
- g) heat-treating said junction layer to reduce resistance between said source/drain structure and said channel layer.
The method according to claim 14, wherein the material of said junction layer is one of a highly doped germanium layer and a highly doped silicon-germanium layer.
Dependencies are inferred from the claim text.