Semiconductor memory device capable of efficient memory cell select operation with reduced element count
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
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Abstract
Four subordinate word lines are driven for a single main word line. In a subordinate word driver circuit, a bank select line activated allows a potential level of a main word line to be transmitted to an internal node via a first transistor. Simultaneously, a select line is also active and a potential level of the internal node is transmitted to a subordinate word line via a second transistor. A bank select line is inactivated and the select line is then further boosted to a boosted potential so that it is driven to a boosted potential of a potential level of the subordinate word line.
Claims14
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns, and divided into a plurality of memory cell blocks in rows and columns;
- a plurality of main word lines in a row direction of said memory cell array, shared by a plurality of said memory cell blocks arranged in the row direction;
- a plurality of subordinate word lines corresponding to memory cell rows in said memory cell blocks, having a first plurality of subordinate word lines provided for each said main word line;
- a main row select circuit provided for said memory cell array, selectively activating said main word in response to an address signal;
- a subordinate row select circuit provided for said memory cell array, indicating a selected subordinate word line of said first plurality of subordinate word lines in response to said address signal;
- a block select circuit indicating a selected memory cell block in response to said address signal;
- a plurality of block select lines activated in response to a selection indication from said block select circuit;
- and
- a plurality of drive circuits each provided for said subordinate word line, each driving a potential of an associated subordinate word line in response to an indication from said subordinate row select circuit and to activation of an associated said block select line and said main word line, each said drive circuit including
- a first switch circuit transmitting a potential level from said main word line in response to activation of said block select line, and
- a hold circuit activated in response to an output level from said first switch circuit and to an indication from said subordinate row select circuit to hold selection indicating information for said associated subordinate word line and drive a potential of said associated subordinate word;
- wherein
- said main row select circuit and said block select circuit reset a level of said main word line and a level of said block select line after said selection indicating information is transmitted to said hold circuit.
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns, and divided into a plurality of memory cell blocks in rows and columns;
- a row select circuit provided for said memory cell array, selecting said memory cell row in response to an address signal;
- a block select circuit indicating a selected memory cell block in response to said address signal;
- a plurality of redundant;
- memory cell blocks provided independently of said memory cell blocks;
- and
- a redundancy determination circuit previously storing a memory cell block and address having a defective memory cell to select a redundant memory cell in said redundant memory cell block when a memory cell designated by an address signal corresponds to said defective memory cell.
Dependencies are inferred from the claim text.