Semiconductor memory device and refreshing method of semiconductor memory device
AssigneeFujitsu Limited
InventorsKazufumi Komura, Takaaki Furuyama, Satoru Kawamoto
Life of this patent
Estimating the term…
Loading patent…
AssigneeFujitsu Limited
InventorsKazufumi Komura, Takaaki Furuyama, Satoru Kawamoto
Estimating the term…
A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. The refresh address counters generate refresh address signals associated with banks in response to a refresh request signal. The switch circuit selectively outputs the external address signal and a refresh address signal generated by one of the refresh address counters in accordance with the refresh request signal. Each of the address holding circuits holds the refresh address signal or the external address signal output from the switch circuit and supplies the held address signal to an associated one of the banks.
A semiconductor memory device comprising:
A method of refreshing a semiconductor memory device having a plurality of banks, comprising the steps of:
A method of refreshing a semiconductor memory device having a plurality of banks, comprising the steps of:
A method of refreshing a semiconductor memory device having a plurality of banks, comprising the steps of:
Dependencies are inferred from the claim text.