Digital switching amplifier
AssigneeSharp Kabushiki Kaisha
InventorMasahiro Kishida
Life of this patent
Estimating the term…
Abstract
A digital switching amplifier in accordance with the present invention is provided with attenuation sections that attenuate respective 1-bit signals that have been subjected to the power amplification, and an offset voltage addition and adjustment section that adds adjustment voltages to output signals of the respective attenuation sections so that a D.C. voltage level difference between negative feedback signals which return to a delta sigma modulation circuit becomes substantially zero. This allows to ensurely provide a digital switching amplifier that can avoid that the gain with respect to positive and negative input signals change and easily avoid that the noise occurs in the lower frequency band due to an offset voltage.
Claims7
A digital switching amplifier in which a first signal and a second signal that is obtained by inverting the first signal are subjected to delta sigma modulation by a delta sigma modulation circuit so as to generate 1-bit signals, respectively, and the 1-bit signals are subjected to power amplification, the first and second signals forming a differential input signal, comprising:
- attenuation sections that attenuate the respective 1-bit signals that have been subjected to the power amplification;
- and
- an offset voltage addition and adjustment section that adds adjustment voltages to output signals of the respective attenuation sections so that a D.C. voltage level difference between negative feedback signals which return to the delta sigma modulation circuit becomes substantially zero.
A digital switching amplifier in which a first signal and a second signal that is obtained by inverting the first signal are subjected to delta sigma modulation by a delta sigma modulation circuit so as to generate 1-bit signals, respectively, and the 1-bit signals are subjected to power amplification, the first and second signals forming a differential input signal, comprising:
- an offset voltage addition and adjustment section that adds adjustment voltages to the 1-bit signals that have been subjected to the power amplification so that a D.C. voltage level difference between negative feedback signals which return to the delta sigma modulation circuit becomes substantially zero;
- and
- attenuation sections that attenuate the respective output signals of the offset voltage addition and adjustment section so as to obtain the negative feedback signals.
A digital switching amplification method, comprising the steps of:
- generating first and second quantization signals by conducting delta sigma modulation with respect to first and second signals whose polarities are different from each other so as to amplify a differential signal constituted by a pair of the first and second signals;
- switching constant voltages supplied from respective constant voltage power sources in accordance with the first and second quantization signals so as to amplify the first and second quantization signals;
- conducting the delta sigma modulation with respect to the first and second quantization signals thus amplified by respective negative feedbacks;
- and
- conducting addition and adjustment of a D.C. offset voltage between the first and second quantization signals so that a D.C. voltage level difference between the first and second quantization signals thus amplified becomes substantially zero.
Dependencies are inferred from the claim text.