Delay circuit applied to semiconductor memory device having auto power-down function

A semiconductor memory device having:

• a cell matrix having a plurality of memory cells;
• a data latch for latching readout data output from said cell matrix;
• an address transfer detection circuit for detecting an address signal change;
• a delay circuit, outputting a latch control signal to said data latch in accordance with an output signal of said address transfer detection circuit, for controlling said data latch to output the readout data in synchronism with the latch control signal, wherein said delay circuit comprises:
• a charge/discharge circuit for moderating a slope of change of an input signal;
• and
• a logic circuit, receiving a charge/discharge signal output from said charge/discharge circuit, for changing an output signal of said logic circuit when the charge/discharge signal exceeds a threshold value of said logic circuit, wherein:
• a time constant in said charge/discharge circuit is varied in accordance with the change in the output signal of said logic circuit.