Semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• an oscillator circuit which generates complementary cycle signals being of a phase difference of about half cycle therebetween and being of a duty ratio of about 50%;
• an output converter which converts the complementary cycle signals outputted from said oscillator circuit to predetermined logic levels and outputs complementary clock signals being of a phase difference of about half cycle therebetween;
• and
• a logic circuit unit which inputs the complementary clock signals outputted from said output converter and performs a logic operation,
• wherein said logic circuit unit includes a duty correction circuit which corrects at least a duty shift between the complementary clock signals, which is developed at said output converter, and recovers the same to about 50%, and
• wherein said duty correction circuit includes:
• a first latch circuit wherein the outputs of one NAND gates are respectively mutually feedback-connected to inputs of the other NAND gates, and complementary clock signals being of the phase difference of about half cycle are supplied to the other inputs of the respective NAND gates, and
• a second latch circuit wherein the outputs of one NAND gates are respectively mutually feedback-connected to inputs of the other NAND gates, and the outputs of the NAND gates of the first latch circuit are respectively supplied to the other inputs of the respective NAND gates.

A semiconductor integrated circuit comprising:

• an oscillator circuit which generates complementary cycle signals being of a phase difference of about half cycle therebetween and being of a duty ratio of about 50%;
• an output converter which converts the complementary cycle signals outputted from said oscillator circuit to predetermined logic levels and outputs complementary clock signals being of a phase difference of about half cycle therebetween;
• and
• a logic circuit unit which inputs the complementary clock signals outputted from said output converter and performs a logic operation,
• wherein said logic circuit unit includes a duty correction circuit which corrects at least a duty shift between the complementary clock signals, which is developed at said output converter, and recovers the same to about 50%, and
• wherein said duty correction circuit includes:
• a first latch circuit wherein the outputs of one NOR gates are respectively mutually feedback-connected to inputs of the other NOR gates, and complementary clock signals being of the phase difference of about half cycle are supplied to the other inputs of the respective NOR gates, and
• a second latch circuit wherein the outputs of one NOR gates are respectively mutually feedback-connected to inputs of the other NOR gates, and the outputs of the NOR gates of the first latch circuit are respectively supplied to the other inputs of the respective NOR gates.

A semiconductor integrated circuit comprising:

• an oscillator circuit which generates complementary cycle signals of a phase difference of about half cycle therebetween and of a duty ratio of about 50%;
• an output converter which converts the complementary cycle signals outputted from said oscillator circuit to predetermined logic levels and outputs complementary clock signals of a phase difference of about half cycle therebetween;
• and
• a logic circuit unit which inputs the complementary clock signals outputted from said output converter and performs a logic operation,
• wherein said logic circuit unit includes a duty correction circuit which corrects at least a duty shift between the complementary clock signals, which is developed at said output converter, and recovers the same to about 50%, and
• wherein said duty correction circuit includes:
• a first logic stage which performs a logic operation for determining a duty ratio for the complementary clock signals, maintaining a period for a first logical value so as to be shorter than a duty ratio of about 50% with respect to complementary clock signals of a duty ratio set to be shorter than the period for the first logical value at a duty ratio at which the period for the first logical value is about 50%, and correcting the period for the first logical value so as to be shorter than the duty ratio of about 50% with respect to complementary clock signals of a duty ratio set to be longer than the period for the first logical value at the duty ratio at which the period for the first logical value is about 50%, and
• a second logic stage which inputs the complementary clock signals outputted from said first logic stage, effects a correction for setting a duty ratio to about 50% thereon and produces an output therefrom.

A semiconductor integrated circuit comprising:

• an oscillator circuit which generates complementary cycle signals being of a phase difference of about half cycle therebetween and being of a duty ratio of about 50%;
• an output converter which converts the complementary cycle signals outputted from said oscillator circuit to predetermined logic levels and outputs complementary clock signals being of a phase difference of about half cycle therebetween;
• and
• a logic circuit unit which inputs the complementary clock signals outputted from said output converter and performs a logic operation,
• wherein said logic circuit unit includes a duty correction circuit which corrects at least a duty shift between the complementary clock signals, which is developed at said output converter, and recovers the same to about 50%, and
• wherein said duty correction circuit includes:
• a first NAND gate which inputs one of complementary clock signals being of a phase difference of about half cycle therebetween and an inverted signal of the other thereof,
• a second NAND gate which inputs the other of the complementary clock signals being of the phase difference of about half cycle therebetween and an inverted signal of the one thereof,
• a first conduction type first transistor switch-controlled by the output of the first NAND gate and connected to a source voltage and an output terminal,
• a second conduction type second transistor switch-controlled by an inverted signal of the output of the second NAND gate and connected to a circuit's ground voltage and the output terminal, and
• a capacitor connected to the output terminal.

A semiconductor integrated circuit comprising:

• an oscillator circuit which generates complementary cycle signals having a phase difference of about half cycle therebetween and having a duty ratio of about 50%;
• an output converter which converts the complementary cycle signals outputted from said oscillator circuit to predetermined logic levels and outputs complementary clock signals having a phase difference of about half cycle therebetween;
• and
• a logic circuit unit which inputs the complementary clock signals outputted from said output converter and performs a logic operation,
• wherein said logic circuit unit includes a duty correction circuit which corrects at least a duty shift between the complementary clock signals, which is developed at said output converter, and recovers the same to about 50%, and
• wherein said duty correction circuit includes:
• a first NAND gate which inputs one of complementary clock signals having a phase difference of about half cycle therebetween and an inverted signal of the other thereof,
• a second NAND gate which inputs the other of the complementary clock signals having the phase difference of about half cycle therebetween and an inverted signal of the one thereof, and
• a latch circuit wherein the output of one NAND gate is mutually feedback-connected to the input of the other NAND gate and the other inputs of the respective NAND gates are respectively supplied with signals outputted from said first and second NAND gates.

A semiconductor integrated circuit comprising:

• an oscillator circuit which generates complementary cycle signals having a phase difference of about half cycle therebetween and having a duty ratio of about 50%;
• an output converter which converts the complementary cycle signals outputted from said oscillator circuit to predetermined logic levels and outputs complementary clock signals having a phase difference of about half cycle therebetween;
• and
• a logic circuit unit which inputs the complementary clock signals outputted from said output converter and performs a logic operation,
• wherein said logic circuit unit includes a duty correction circuit which corrects at least a duty shift between the complementary clock signals, which is developed at said output converter, and recovers the same to about 50%, and
• wherein said duty correction circuit includes:
• flip-flops which respectively divide complementary clock signals having a phase difference of about half cycle therebetween into two, and
• a logic gate circuit which receives the outputs of said flip-flops as two inputs, brings the clock signals into status changes each time the two inputs coincide or uncoincide, and outputs the state-changed signals therefrom.

A semiconductor integrated circuit comprising:

• an oscillator circuit which generates complementary cycle signals having a phase difference of about half cycle therebetween and having a duty ratio of about 50%;
• an output converter which converts the complementary cycle signals outputted from said oscillator circuit to predetermined logic levels and outputs complementary clock signals having a phase difference of about half cycle therebetween;
• and
• a logic circuit unit which inputs the complementary clock signals outputted from said output converter and performs a logic operation,
• wherein said logic circuit unit includes a duty correction circuit which corrects at least a duty shift between the complementary clock signals, which is developed at said output converter, and recovers the same to about 50%, and
• wherein said duty correction circuit includes a first logic stage which inputs the complementary clock signals having passed said output converter, and a second logic stage which inputs the output of said first logic stage,
• wherein said first logic stage performs a logic operation for determining a duty ratio for the complementary clock signals, correcting complementary clock signals of a duty ratio set to be shorter than a period for a first logical value at a duty ratio at which the period for the first logical value is about 50%, to a duty ratio of about 50% or maintaining the period for the first logical value so as to be shorter than the duty ratio of about 50%, and correcting the period for the first logical value so as to be shorter than the duty ratio of about 50% with respect to complementary clock signals of a duty ratio set to be longer than the period for the first logical value at the duty ratio at which the period for the first logical value is about 50%, and
• wherein said second logic stage inputs complementary clock signals outputted from said first logic stage, brings a duty ratio thereof to about 50% and produces an output therefrom.