# US 2001/0043101 A1 · Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2001/0043101 A1 - Document ID: US20010043101A1 - Status: Published application - Kind: A1 - Application number: 09/919,926 - Filed: 2001-08-02 - Published: 2001-11-22 - Earliest claimed: 1997-07-02 - Assignees: Canon Kabushiki Kaisha - Inventors: Katsuhisa Ogawa; Tadahiro Ohmi; Tadashi Shibata - Web page: https://patentgrep.com/patent/US20010043101A1 ## CPC - H03K 3/0315: {Ring oscillators} - H03K 5/133: using a chain of active delay devices - H03L 7/0812: {and where no voltage or current controlled oscillator is used} - H03L 7/0995: {the oscillator comprising a ring oscillator} - H03K 3/354: Astable circuits - H03K 2005/00045: {DC voltage control of a capacitor or of the coupling of a capacitor as a load} - H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output. ## Claims ### Claim 1 A semiconductor integrated circuit comprising a circuit unit, said circuit unit comprising: an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof; and first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal; wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal. ### Claim 2 (depends on 1) The semiconductor integrated circuit according to claim 1, further comprising an inverter connected to the output terminal of said circuit unit. ### Claim 3 (depends on 1) The semiconductor integrated circuit according to claim 1, comprising a plurality of said circuit units and a plurality of inverters respectively connected to output terminals of said circuit units, wherein an output terminal of each said inverter is connected to an input terminal of each said circuit unit. ### Claim 4 (depends on 3) The semiconductor integrated circuit according to claim 3, wherein the control terminals of the circuit units are connected to each other. ### Claim 5 (depends on 3) The semiconductor integrated circuit according to claim 3, wherein an output of an inverter associated with the circuit unit of the final stage out of the output terminals of the inverters to the circuit units is a final output terminal. ### Claim 6 (depends on 1) The semiconductor integrated circuit according to claim 1, comprising a plurality of said circuit units, wherein an output terminal of each said circuit unit is connected to an input terminal of a circuit unit of a next stage. ### Claim 7 (depends on 6) The semiconductor integrated circuit according to claim 6, wherein the control terminals of the circuit units of odd stages are connected to each other and the control terminals of the circuit units of even stages are connected to each other. ### Claim 8 (depends on 6) The semiconductor integrated circuit according to claim 6, comprising an odd number of said circuit units. ### Claim 9 (depends on 7) The semiconductor integrated circuit according to claim 7, comprising an odd number of said circuit units. ### Claim 10 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the one terminals of said first and second capacitor means are connected through a current mirror circuit to the gate electrodes of the NMOS transistor and the PMOS transistor. ### Claim 11 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein a connection point between the one terminals of the first and second capacitor means and the gate electrodes of the NMOS transistor and the PMOS transistor is in a floating state. ### Claim 12 (depends on 1) The semiconductor integrated circuit according to claim 1, comprising a first transistor whose gate electrode is connected to the one terminals of the first and second capacitor means; a second transistor whose source terminal is connected to a source terminal of the first transistor; a third transistor whose drain terminal is connected to a drain terminal of the first transistor, said third transistor having a gate terminal and the drain terminal shorted; a fourth transistor forming a current mirror circuit with the third transistor; a fifth transistor whose drain terminal is connected to a drain terminal of the second transistor, said fifth transistor having a gate terminal and the drain terminal shorted; a sixth transistor forming a current mirror circuit with the fifth transistor; a seventh transistor whose drain terminal is connected to a drain terminal of the sixth transistor, said seventh transistor having the drain terminal and a gate terminal shorted; and an eighth transistor forming a current mirror circuit with the seventh transistor; wherein a drain terminal of the fourth transistor and a drain terminal of the eighth transistor are connected to each other to be connected to the gate electrodes of said NMOS transistor and said PMOS transistor. ### Claim 13 (depends on 12) The semiconductor integrated circuit according to claim 12, wherein the source terminal of the first transistor is a terminal connected to a low voltage supply whose one terminal is grounded, source terminals of the third, fourth, fifth, and sixth transistors are terminals connected to a power supply to which said PMOS transistor is connected, and source terminals of the seventh and eighth transistors are ground terminals. ### Claim 14 (depends on 13) The semiconductor integrated circuit according to claim 13, wherein said first, second, seventh, and eighth transistors are NMOS transistors and said third, fourth, fifth, and sixth transistors are PMOS transistors. ### Claim 15 A delay-locked loop comprising: a semiconductor integrated circuit comprising a circuit unit, said circuit unit comprising an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal, wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal; a phase comparator to which a reference clock and an output from the output terminal of said semiconductor integrated circuit are input; and a low-pass filter to which a phase difference resulting from comparison in said phase comparator is input; wherein an output of said lower-pass filter is input to the control terminal of said semiconductor integrated circuit. ### Claim 16 (depends on 15) The delay-locked loop according to claim 15, further comprising an inverter connected to the output terminal of said circuit unit of the semiconductor integrated circuit. ### Claim 17 (depends on 15) The delay-locked loop according to claim 15, comprising a plurality of said circuit units of the semiconductor integrated circuit and a plurality of inverters respectively connected to output terminals of said circuit units, wherein an output terminal of each said inverter is connected to an input terminal of each said circuit unit. ### Claim 18 (depends on 17) The delay-locked loop according to claim 17, wherein the control terminals of the circuit units of the semiconductor integrated circuit are connected to each other. ### Claim 19 (depends on 17) The delay-locked loop according to claim 17, wherein an output of an inverter associated with the circuit unit of the final stage out of the output terminals of the inverters to the circuit units of the semiconductor integrated circuit is a final output terminal. ### Claim 20 (depends on 15) The delay-locked loop according to claim 15, comprising a plurality of said circuit units of the semiconductor integrated circuit, wherein an output terminal of each said circuit unit is connected to an input terminal of a circuit unit of a next stage. ### Claim 21 (depends on 20) The delay-locked loop according to claim 20, wherein the control terminals of the circuit units of odd stages of the semiconductor integrated circuit are connected to each other and the control terminals of the circuit units of even stages thereof are connected to each other. ### Claim 22 (depends on 20) The delay-locked loop according to claim 20, comprising an odd number of said circuit units of the semiconductor integrated circuit. ### Claim 23 (depends on 21) The delay-locked loop according to claim 21, comprising an odd number of said circuit units of the semiconductor integrated circuit. ### Claim 24 (depends on 15) The delay-locked loop according to claim 15, wherein the one terminals of said first and second capacitor means of the semiconductor integrated circuit are connected through a current mirror circuit to the gate electrodes of the NMOS transistor and the PMOS transistor. ### Claim 25 (depends on 15) The delay-locked loop according to claim 15, wherein a connection point between the one terminals of the first and second capacitor means of the semiconductor integrated circuit and the gate electrodes of the NMOS transistor and the PMOS transistor thereof is in a floating state. ### Claim 26 (depends on 15) The delay-locked loop according to claim 15, comprising a first transistor whose gate electrode is connected to the one terminals of the first and second capacitor means of the semiconductor integrated circuit; a second transistor whose source terminal is connected to a source terminal of the first transistor; a third transistor whose drain terminal is connected to a drain terminal of the first transistor, said third transistor having a gate terminal and the drain terminal shorted; a fourth transistor forming a current mirror circuit with the third transistor; a fifth transistor whose drain terminal is connected to a drain terminal of the second transistor, said fifth transistor having a gate terminal and the drain terminal shorted; a sixth transistor forming a current mirror circuit with the fifth transistor; a seventh transistor whose drain terminal is connected to a drain terminal of the sixth transistor, said seventh transistor having the drain terminal and a gate terminal shorted; and an eighth transistor forming a current mirror circuit with the seventh transistor; wherein a drain terminal of the fourth transistor and a drain terminal of the eighth transistor are connected to each other to be connected to the gate electrodes of said NMOS transistor and said PMOS transistor. ### Claim 27 (depends on 26) The delay-locked loop according to claim 26, wherein the source terminal of the first transistor of the semiconductor integrated circuit is a terminal connected to a low voltage supply whose one terminal is grounded, source terminals of the third, fourth, fifth, and sixth transistors are terminals connected to a power supply to which said PMOS transistor is connected, and source terminals of the seventh and eighth transistors are ground terminals. ### Claim 28 (depends on 27) The delay-locked loop according to claim 27, wherein said first, second, seventh, and eighth transistors of the semiconductor integrated circuit are NMOS transistors and said third, fourth, fifth, and sixth transistors are PMOS transistors. ### Claim 29 A self-synchronizing pipeline type system comprising: a semiconductor integrated circuit comprising a circuit unit, said circuit unit comprising an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal, wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal; an input latch; a signal processing logic circuit; an output latch; and first and second handshake circuits; wherein digital input data and an output from the first handshake circuit are input to said input latch, data from said input latch is input to said signal processing logic circuit, an output from said signal processing logic circuit and an output from said second handshake circuit are input to the output latch, a clock signal output from the first handshake circuit is input to the control terminal of said semiconductor integrated circuit, and an output from said semiconductor integrated circuit is input to the second handshake circuit. ### Claim 30 (depends on 29) The system according to claim 29, further comprising an inverter connected to the output terminal of said circuit unit of the semiconductor integrated circuit. ### Claim 31 (depends on 29) The system according to claim 29, comprising a plurality of said circuit units of the semiconductor integrated circuit and a plurality of inverters respectively connected to output terminals of said circuit units, wherein an output terminal of each said inverter is connected to an input terminal of each said circuit unit. ### Claim 32 (depends on 31) The system according to claim 31, wherein the control terminals of the circuit units of the semiconductor integrated circuit are connected to each other. ### Claim 33 (depends on 31) The system according to claim 31, wherein an output of an inverter associated with a circuit unit of the final stage out of the outputs of the inverters to the circuit units of the semiconductor integrated circuit is a final output terminal. ### Claim 34 (depends on 29) The system according to claim 29, comprising a plurality of said circuit units of the semiconductor integrated circuit, wherein an output terminal of each said circuit unit is connected to an input terminal of a circuit unit of a next stage. ### Claim 35 (depends on 34) The system according to claim 34, wherein the control terminals of the circuit units of odd stages of the semiconductor integrated circuit are connected to each other and the control terminals of the circuit units of even stages thereof are connected to each other. ### Claim 36 (depends on 34) The system according to claim 34, comprising an odd number of said circuit units of the semiconductor integrated circuit. ### Claim 37 (depends on 35) The system according to claim 35, comprising an odd number of said circuit units of the semiconductor integrated circuit. ### Claim 38 (depends on 29) The system according to claim 29, wherein the one terminals of said first and second capacitor means of the semiconductor integrated circuit are connected through a current mirror circuit to the gate electrodes of the NMOS transistor and the PMOS transistor. ### Claim 39 (depends on 29) The system according to claim 29, wherein a connection point between the one terminals of the first and second capacitor means of the semiconductor integrated circuit and the gate electrodes of the NMOS transistor and the PMOS transistor thereof is in a floating state. ### Claim 40 (depends on 29) The system according to claim 29, comprising a first transistor whose gate electrode is connected to the one terminals of the first and second capacitor means of the semiconductor integrated circuit; a second transistor whose source terminal is connected to a source terminal of the first transistor; a third transistor whose drain terminal is connected to a drain terminal of the first transistor, said third transistor having a gate terminal and the drain terminal shorted; a fourth transistor forming a current mirror circuit with the third transistor; a fifth transistor whose drain terminal is connected to a drain terminal of the second transistor, said fifth transistor having a gate terminal and the drain terminal shorted; a sixth transistor forming a current mirror circuit with the fifth transistor; a seventh transistor whose drain terminal is connected to a drain terminal of the sixth transistor, said seventh transistor having the drain terminal and a gate terminal shorted; and an eighth transistor forming a current mirror circuit with the seventh transistor; wherein a drain terminal of the fourth transistor and a drain terminal of the eighth transistor are connected to each other to be connected to the gate electrodes of said NMOS transistor and said PMOS transistor. ### Claim 41 (depends on 40) The system according to claim 40, wherein the source terminal of the first transistor of the semiconductor integrated circuit is a terminal connected to a low voltage supply whose one terminal is grounded, source terminals of the third, fourth, fifth, and sixth transistors are terminals connected to a power supply to which said PMOS transistor is connected, and source terminals of the seventh and eighth transistors are ground terminals. ### Claim 42 (depends on 41) The system according to claim 41, wherein said first, second, seventh, and eighth transistors of the semiconductor integrated circuit are NMOS transistors and said third, fourth, fifth, and sixth transistors are PMOS transistors. ### Claim 43 A voltage-controlled oscillator comprising: a plurality of circuit units, each said circuit unit comprising an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal, wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal; wherein an output terminal of each said circuit unit is connected to an input terminal of a circuit unit of a next stage, an input terminal of the circuit unit of the first stage is connected to an output terminal of the circuit unit of the final stage, the control terminals of the circuit units of the first stage and the final stage are connected to each other, and the control terminals of the circuit units except for the first stage and the final stage are connected to each other. ### Claim 44 A phase-locked loop comprising: a voltage-controlled oscillator comprising a plurality of circuit units, each said circuit unit comprising an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal, wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal, and wherein an output terminal of each said circuit unit is connected to an input terminal of a circuit unit of a next stage, an input terminal of the circuit unit of the first stage is connected to an output terminal of the circuit unit of the final stage, the control terminals of the circuit units of the first stage and the final stage are connected to each other, and the control terminals of the circuit units except for the first stage and the final stage are connected to each other; a phase comparator to which a signal of a frequency fO is input; and a low-pass filter to which an output from said phase comparator is input; wherein an output from said low-pass filter is input to the control terminal of said voltage-controlled oscillator and an output from said voltage-controlled oscillator is input to said phase comparator. ### Claim 45 A semiconductor integrated circuit wherein a signal input terminal is connected through first capacitor means to an input terminal of a sense amplifier and a control input terminal is connected through second capacitor means to the input terminal of said sense amplifier, wherein a common connection point between the input terminal of said sense amplifier and said first and second capacitor means is a floating node, and wherein a signal applied through said signal input terminal to the input terminal of said sense amplifier is vertically shifted by a control signal applied to said control input terminal, at least, near a determination threshold of said sense amplifier, thereby controlling a delay amount of an output. ### Claim 46 (depends on 45) The semiconductor integrated circuit according to claim 45, wherein said sense amplifier has a buffer function, wherein a plurality of said semiconductor integrated circuits are connected in series so that an output terminal of a semiconductor integrated circuit of a preceding stage is connected to a signal input terminal of a semiconductor integrated circuit of a next stage, the control input terminals of the all semiconductor integrated circuits connected in series being connected to each other, and wherein a signal is applied to the signal input terminal of the first stage out of the semiconductor integrated circuits connected in series and the output terminal of the semiconductor integrated circuit of the final stage is a signal output terminal. ### Claim 47 (depends on 45) The semiconductor integrated circuit according to claim 45, wherein said sense amplifier has an inverter function, wherein a plurality of said semiconductor integrated circuits are connected in series so that an output terminal of a semiconductor integrated circuit of a preceding stage is connected to a signal input terminal of a semiconductor integrated circuit of a next stage, the control input terminals of the semiconductor integrated circuits of odd stages out of said plurality of semiconductor integrated circuits connected in series are connected to each other, and the control input terminals of the semiconductor integrated circuits of even stages are connected to each other, and wherein a signal is applied to the signal input terminal of the first stage out of the semiconductor integrated circuits connected in series and the output terminal of the semiconductor integrated circuit of the final stage is a signal output terminal. ### Claim 48 (depends on 47) The semiconductor integrated circuit according to claim 47, wherein control voltages changing in opposite directions to each other are applied to the control input terminals of the semiconductor integrated circuits of said odd stages and to the control input terminals of the semiconductor integrated circuits of said even stages. ### Claim 49 (depends on 45) The semiconductor integrated circuit according to claim 45, wherein said sense amplifier is comprised of a complementary MOS inverter. ### Claim 50 (depends on 45) The semiconductor integrated circuit according to claim 45, wherein said sense amplifier is a comparator having an input stage of a differential amplifier comprised of MOS transistors. ### Claim 51 (depends on 50) The semiconductor integrated circuit according to claim 50, wherein an input-output relation of said comparator is an inverting relation. ### Claim 52 (depends on 50) The semiconductor integrated circuit according to claim 50, wherein an input-output relation of said comparator is a non-inverting relation. ### Claim 53 (depends on 49) The semiconductor integrated circuit according to claim 49, wherein the MOS transistor forming said sense amplifier and the first and second capacitor means are comprised of a transistor wherein a floating electrode is formed through a first gate insulating film on a channel region between source and drain regions spaced from each other on a semiconductor substrate and wherein two gate electrodes electrically insulated from each other are formed through a second gate oxide film on said floating gate electrode. ### Claim 54 (depends on 45) A voltage control delay line comprising the semiconductor integrated circuit as set forth in claim 45, wherein a delay amount of an output pulse is controlled by controlling a pulse applied to said signal input terminal by said control input terminal. ### Claim 55 (depends on 54) A delay-locked loop comprising the voltage control delay line as set forth in claim 54. ### Claim 56 (depends on 54) A self-synchronizing pipeline type system comprising the voltage control delay line as set forth in claim 54. ### Claim 57 (depends on 47) A voltage-controlled oscillator wherein an odd number of semiconductor integrated circuits as set forth in claim 47 are connected in series and a final output terminal is connected to the signal input terminal of the first stage, thereby forming an oscillation loop, and wherein an oscillation frequency is controlled by control signals supplied through the control input terminals of the semiconductor integrated circuits of odd stages and through the control input terminals of the semiconductor integrated circuits of even stages. ### Claim 58 (depends on 57) A phase-locked loop comprising the voltage-controlled oscillator as set forth in claim 57.