Integrated circuit device incorporating dll circuit

An integrated circuit device having a DLL circuit that generates a control clock whose phase is regulated by delaying a reference clock, wherein:

• said DLL circuit comprises a plurality of variable delay circuits that transmit said reference clock and a plurality of first internal power source circuits supplied with external power source and that generate a first internal power source lower than said external power source;
• and
• said plurality of variable delay circuits are supplied with said first internal power source from respectively different first internal power source circuits.

An integrated circuit device comprising:

• a DLL circuit that generates a control clock whose phase is regulated by delaying a reference clock, wherein:
• said DLL circuit comprises a variable delay circuit that transmits said reference clock and a first internal power source circuit that is supplied with external power source and that generates a first internal power source lower than said external power source, and
• said variable delay circuit comprises a delay unit and a drive unit that drives said delay unit, said delay unit being supplied with said first internal power source from said first internal power source circuit and said drive unit being supplied with power source different from said first internal power source.

An integrated circuit device comprising:

• a DLL circuit that generates a control clock whose phase is regulated by delaying a reference clock, wherein:
• said DLL circuit comprises a variable delay circuit that transmits said reference clock and a first internal power source circuit that is supplied with external power source and that generates a first internal power source lower than said external power source, and
• said variable delay circuit comprises a delay unit and an output unit that outputs a clock delayed by said delay unit, said delay unit being supplied with said first internal power source from said first internal power source circuit and said output unit being supplied with power source different from said first internal power source.

An integrated circuit device comprising a DLL circuit that generates a control clock whose phase is regulated by delaying a reference clock, comprising:

• a first external power source that is supplied to said DLL circuit and a second external power source that is supplied to a prescribed circuit other than said DLL circuit;
• said DLL circuit comprising a plurality of variable delay circuits that transmit said reference clock and a phase comparator that detects whether the phase difference of the delayed clock and said reference clock is less than a prescribed value, and a plurality of first internal power source circuits that are supplied with said first external power source and a prescribed control voltage and that generate first internal power source lower than the first external power source;
• said variable delay circuits and/or said phase comparator being respectively supplied with said first internal power source from different first internal power source circuits.

An integrated circuit device comprising:

• a DLL circuit that generates a control clock whose phase is regulated by delaying a reference clock, wherein said DLL circuit comprises a variable delay circuit having a delay unit that transmits said reference clock and a phase coincidence detection unit that detects when the phase difference of the delayed clock and said reference clock is less than a prescribed value;
• and
• a supply wiring of a first back bias power source that is supplied to the channel of a transistor constituting said delay unit or a transistor constituting the phase coincidence detection unit is isolated from a supply wiring of a second back bias power source that is supplied to the channel of a transistor of another circuit.

An integrated circuit device comprising a DLL circuit that generates a control clock that is regulated in phase by delaying a reference clock, comprising:

• a plurality of clock signal wirings that respectively supply said control clock to a plurality of internal circuits and are formed of practically equal length;
• and
• a buffer circuit provided between a branch lead and a branch point on said clock signal wiring and amplifying said control clock which is propagated to it.