Phase lock loop system and method
AssigneeHoneywell International Inc.
InventorsKevin Wayne Locker, Joseph Murray
Life of this patent
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Abstract
Symmetrical cross coupled PLL circuits provide pseudo-synchronization between two independent clock signals, especially for use in fault tolerant applications. Independent oscillators provide input signals to each of the PLL circuits. The PLL circuits include divide circuitry that provide output signals at some sub multiple of the input clock signals. The phase relationship between the output clock signals from the cross coupled PLL circuits is monitored by phase detector circuits. If the phase of one output clock signal is determined to be advanced relative to the other output clock signal, the phase of that output clock signal is retarded by temporarily increasing the divide ratio of the PLL circuit producing the phase advanced signal.
Claims19
A system for maintaining two clocks in pseudo-synchronization comprising:
- first and second oscillators, each providing a periodic signal of nominal frequency and phase;
- first and second cross coupled PLL circuits, the first PLL circuit having an input to receive the periodic signal from the first oscillator, and the second PLL circuit having an input to receive the periodic signal from the second oscillator, each of the first and second PLL circuits including a divider circuit for dividing the nominal frequency of the periodic signal received thereby by a divide ratio to generate a first output signal at an output of the first PLL circuit and a second output signal at an output of the second PLL circuit;
- and
- first and second phase detectors capable of measuring the relative phase relationship of the first and second output signals and temporarily increasing the divide ratio of the divider circuit of one of the first and second PLL circuits in response to detecting that the phase of the output signal from such PLL circuit is advanced relative to the phase of the output signal from the other of the first and second PLL circuits.
A method for maintaining two clock signals in pseudo-synchronization comprising the steps of:
- providing first and second clock signals having a nominal frequency and phase;
- applying the first and second clock signals to inputs of first and second PLL circuits;
- dividing the frequency of each of the first and second clock signals by a divisor n to produce an output clock signal having a frequency equal to the nominal frequency divided by n at an output of each of the first and second PLL circuits;
- comparing the phase of the output clock signal from the first PLL circuit to the phase of the output clock signal from the second PLL circuit;
- temporarily increasing the divisor n in the first PLL circuit if the phase of the output signal from the first PLL circuit is advanced by more than a predetermined amount compared to the phase of the output signal from the second PLL circuit;
- and
- temporarily increasing the divisor n in the second PLL circuit if the phase of the output signal from the second PLL circuit is advanced by more than a predetermined amount compared to the phase of the output signal from the first PLL circuit.
A method for maintaining two clock signals in pseudo-synchronization comprising the steps of:
- providing a first PLL circuit coupled to a first clock oscillator and producing a first output clock signal;
- providing a second PLL circuit coupled to a second clock oscillator and producing a second output clock signal;
- measuring the relative phase relationship between the first and second output clock signals;
- and
- retarding the phase of the more advanced of the first or second output clock signals if the relative relationship exceeds a predetermined value.
A method of maintaining two clock signals in pseudo-synchronization with each other and with a system synchronization signal comprising the steps of:
- providing a first PLL circuit coupled to a first clock oscillator and producing a first output clock signal;
- providing a second PLL circuit coupled to a second clock oscillator and producing a second output clock signal;
- measuring the relative phase relationship between the first and second output clock signals;
- retarding the phase of the more advanced of the first or second output clock signals if the relative relationship exceeds a predetermined value;
- synchronizing the first output clock signal to a system synchronization signal if the first output clock signal is advanced with respect to the system synchronization signal by retarding the phase of the first output clock signal at a predetermined time after detecting the system synchronization signal;
- and
- decreasing the predetermined time in response to a signal related to the second output clock signal indicating the second output clock signal is advanced from the system synchronization signal by an amount less than the amount the first output clock signal is advanced with respect to the system synchronization signal.
A system for maintaining a plurality of clock signals in pseudo-ynchronization comprising:
- a plurality of oscillators each providing a clock signal having a nominal frequency nf;
- a plurality of PLL circuits, each of the PLL circuits having an input coupled to one of the plurality of oscillators for receiving a clock signal, each of the PLL circuits providing an output clock signal having a nominal frequency f at a first output and a sample clock signal having a nominal frequency (1/m) f at a second output;
- and
- a phase detector capable of measuring the relative phase relationship between the plurality of sample clock signals and of retarding the phase of one of the plurality of output clock signals provided by one of the plurality of PLL circuits in response to a sample clock signal provided by such one of the plurality of PLL circuits having a phase advanced with respect to any other sample clock signal by more than a predetermined value.
A method for transmitting data from a first channel to a second channel, each of the first and second channels having a clock, the clocks of the first and second channels being pseudo-synchronized, the method comprising the steps of:
- transferring data into a first storage element of the first channel when the clock in the first channel is low;
- transferring data into a second storage element of the first channel when the clock in the first channel is high;
- transferring data out of the first storage element to the second channel when the clock in the second channel is high;
- and
- transferring data out of the second storage element to the second channel when the clock in the second channel is low.
A circuit for transferring data from a first channel to a second channel pseudo-synchronized with the first channel, the circuit comprising:
- a first channel clock associated with the first channel pseudo-synchronized to a second channel clock associated with the second channel;
- a first input for receiving data;
- first and second storage elements coupled to the first input through first and second multiplexers, the first multiplexer coupled to transfer data from the first input to the first storage element when the first channel clock is in a low state and the second multiplexer coupled to transfer data from the first input to the second storage element when the first channel clock is in a high state;
- and
- a third multiplexer coupled to an output of each of the first and second storage elements and having a multiplexer output coupled to transfer data to the second channel, the third multiplexer transferring data from the first storage element to the multiplexer output when the second channel clock is in a high state and transferring data from the second storage element to the multiplexer output when the second channel clock is in a low state.
Dependencies are inferred from the claim text.