US 2001/0043097 A1 · Sync signal generating circuit provided in semiconductor integrated circuit · patentgrep

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Abstract

A sync signal generating circuit has a first I/O replica for delaying an external clock signal, a comparator replica with a variable delay time for delaying an output of the first I/O replica, a first ramp-voltage generating circuit for outputting a first voltage whose potential level begins to rise at a time of transition of a level of the output of the comparator replica and stops rising at a predetermined timing, a second ramp-voltage generating circuit for outputting a second voltage whose potential level begins to rise after the rising of the potential level of the first voltage stops, a voltage comparator for comparing the first and second voltages and outputting an internal clock signal, a second I/O replica for delaying the internal clock signal with a delay time substantially equal to the delay time of the first I/O replica, and a phase comparator for comparing a phase of an output of the second I/O replica and a phase of an input to the first I/O replica. A delay time in the comparator replica is adjusted on the basis of an output from the phase comparator.

Claims30

Dependent claims

A sync signal generating circuit comprising:

an input buffer circuit to which an external clock signal is input;
a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output;
a variable delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit and delivering a delayed output;
a first voltage generating circuit, connected to the variable delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the variable delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit;
a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit;
a voltage comparing circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages and outputting an internal clock signal;
an internal circuit connected to the voltage comparing circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal;
a second delay circuit, connected to the voltage comparing circuit, for delaying the internal clock signal by a second time period that is substantially equal to said first time period, and delivering a delayed output;
and
a phase comparator, connected to the second delay circuit and the input buffer circuit, for comparing phases of outputs of the second delay circuit and the input buffer circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs,
wherein a delay time in said variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

8 more elements

A sync signal generating circuit comprising:

an input buffer circuit to which an external clock signal is input;
a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output;
a variable delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit and delivering a delayed output;
a first voltage generating circuit, connected to the variable delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the variable delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit;
a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit;
a voltage comparing circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages and outputting an internal clock signal;
an internal circuit connected to the voltage comparing circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal;
a first frequency-division circuit, connected to the voltage comparing circuit, for frequency-dividing the internal clock signal and delivering a frequency-division output;
a second delay circuit, connected to the first frequency-division circuit, for delaying the output of the first frequency-division circuit by a second time period that is substantially equal to said first time period, and delivering a delayed output;
a second frequency-division circuit, connected to the input buffer circuit, for frequency-dividing the output of the input buffer circuit and delivering a frequency-division output;
and
a phase comparator, connected to the second delay circuit, the second frequency-division circuit and the variable delay circuit, for comparing phases of outputs of the second delay circuit and the second frequency-division circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs to the variable delay circuit,
wherein a delay time in said variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

10 more elements

A sync signal generating circuit comprising:

an input buffer circuit to which an external clock signal is input;
a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output;
a second delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit by a second time period and delivering a delayed output;
a first voltage generating circuit, connected to the second delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the second delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit;
a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit;
a voltage comparing/variable delay circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages, outputting an internal clock signal, delaying the internal clock signal, and delivering a delayed output;
an internal circuit connected to the voltage comparing/variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal;
a third delay circuit, connected to the voltage comparing/variable delay circuit, for delaying the internal clock signal by a time period that is substantially equal to said first time period, and delivering a delayed output;
and
a phase comparator, connected to the third delay circuit and the input buffer circuit, for comparing phases of outputs of the third delay circuit and the input buffer circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs,
wherein a delay time in said voltage comparing/variable delay circuit is adjusted on the basis of the control signal corresponding to the phase difference, which is output from the phase comparator.

8 more elements

A sync signal generating circuit comprising:

an input buffer circuit to which an external clock signal is input;
a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output;
a second delay circuit, connected to the first delay circuit, for delaying the output of the first delay circuit by a second time period and delivering a delayed output;
a first voltage generating circuit, connected to the second delay circuit and the input buffer circuit, for outputting a first analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the second delay circuit, and stops rising at a time of transition of a level of the output of the input buffer circuit;
a second voltage generating circuit, connected to the input buffer circuit, for outputting a second analog voltage whose potential level begins to rise at a predetermined gradient at a time of transition of a level of the output of the input buffer circuit;
a voltage comparing/variable delay circuit, connected to the first and second voltage generating circuits, for comparing the first and second analog voltages, outputting an internal clock signal, delaying the internal clock signal, and delivering a delayed output;
an internal circuit connected to the voltage comparing/variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal;
a first frequency-division circuit, connected to the voltage comparing/variable delay circuit, for frequency-dividing the internal clock signal and delivering a frequency-division output;
a third delay circuit, connected to the first frequency-division circuit, for delaying the output of the first frequency-division circuit by a third time period that is substantially equal to said first time period, and delivering a delayed output;
a second frequency-division circuit, connected to the input buffer circuit, for frequency-dividing the output of the input buffer circuit and delivering a frequency-division output;
and
a phase comparator, connected to the third delay circuit, the second frequency-division circuit and the voltage comparing/variable delay circuit, for comparing phases of outputs of the third delay circuit and the second frequency-division circuit, and outputting a control signal corresponding to a phase difference obtained by the comparison of the outputs to the voltage comparing/variable delay circuit,
wherein a delay time in said voltage comparing/variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

10 more elements

A sync signal generating circuit comprising:

an input buffer circuit to which an external clock signal is input;
a first delay circuit, connected to the input buffer circuit, for delaying an output of the input buffer circuit by a first time period and delivering a delayed output;
a second delay circuit, connected to the first delay circuit and the input buffer circuit, for starting delaying of the output of the first delay circuit at a time of transition of a level of the output of the first delay circuit and stopping the delaying of the output of the first delay circuit at a time of transition of a level of the output of the input buffer circuit;
a third delay circuit, connected to the input buffer circuit, for starting delaying of the output of the input buffer circuit at a time of transition of a level of the output of the input buffer circuit, delaying the output of the input buffer circuit by a delay time substantially equal to a delay time in the second delay circuit, and outputting a delayed output;
a variable delay circuit, connected to the third delay circuit, for delaying the output of the third delay circuit and outputting an internal clock signal;
an internal circuit connected to the variable delay circuit, an operation of the internal circuit being controlled in synchronism with the internal clock signal;
a fourth delay circuit, connected to the variable delay circuit, for delaying the internal clock signal by a time period that is substantially equal to said first time period, and delivering a delayed output;
and
a phase comparator, connected to the fourth delay circuit and the input buffer circuit, for comparing phases of outputs of the fourth delay circuit and the input buffer circuit, and outputting to the variable delay circuit a control signal corresponding to a phase difference obtained by the comparison of the outputs,
wherein a delay time in said variable delay circuit is adjusted on the basis of the control signal output from the phase comparator.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/846,286Filed 2 May 2001
Priority: JP 2000-15025422 May 2000
Published: 22 Nov 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 7/04
Arrangements for writing information into, or reading information out from, a digital store: with means for avoiding disturbances due to…
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
H03L 7/0812
Provided with an additional controlled phase shifter: and where no voltage or current controlled oscillator is used

Family

US 6,373,303 B1Related patent
US 2001/0043097 A1This patent

From the US filing history. Foreign family members aren’t listed.

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