Dram sense amplifier for low voltages

A sense amplifier, comprising:

• a pair of cross-coupled inverters, wherein each inverter includes:
• a p-channel metal oxide semiconductor (PMOS) transistor;
• and
• a pair of n-channel metal oxide semiconductor (NMOS) transistors coupled at a drain region and a source region, and wherein a drain region of the PMOS transistor is coupled to the drain region for the pair of NMOS transistors;
• a bit line coupled to each inverter, wherein each bit line couples to a gate for a first one of the pair of NMOS transistors in each inverter;
• and
• a pair of output transmission lines, wherein each one of the pair of output transmission lines is coupled to the drain region for the PMOS and the NMOS transistors.

A latch circuit, comprising:

• a pair of cross-coupled amplifiers, wherein each amplifier includes:
• a first transistor of a first conductivity type;
• a second transistor and a third transistor of a second conductivity type, wherein the second and third transistors are coupled at a drain region and are coupled at a source region, and wherein the drain region for the second and third transistors are coupled to a drain region of the first transistor;
• a pair of input transmission lines, wherein each one of the pair of input transmission lines is coupled to a gate of the second transistor in each amplifier;
• and
• a pair of output transmission lines, wherein each one of the pair of output transmission lines is coupled to the drain region of the first transistor and to the drain region of the second and the third transistors.

An amplifier circuit, comprising:

• a pair of cross-coupled inverters, wherein each inverter includes:
• a transistor of a first conductivity type;
• a dual-gated metal-oxide semiconducting field effect transistor (MOSFET) of a second conductivity type, wherein the first transistor of a first conductivity type and the a dual-gated MOSFET are coupled at a drain region;
• a pair of input transmission lines, wherein each one of the pair of input transmission lines is coupled to a first gate of the dual-gated MOSFET;
• and
• a pair of output transmission lines, wherein each one of the pair of output transmission lines is coupled to the drain region on each one of the pair of cross-coupled inverters.

A memory circuit, comprising:

• a number of memory arrays;
• at lease one sense amplifier, wherein the sense amplifier includes:
• a pair of cross-coupled inverters, wherein each inverter includes:
• a p-channel metal oxide semiconductor (PMOS) transistor;
• and
• a pair of n-channel metal oxide semiconductor (NMOS) transistors coupled at a drain region and a source region, and wherein a drain region of the PMOS transistor is coupled to the drain region for the pair of NMOS transistors;
• a complementary pair of bit lines coupling the at least one sense amplifier to a number of memory cells in the number of memory arrays, and wherein each one of the complementary pair of bit lines couples to a gate of a first one of the pair of NMOS transistors in each inverter;
• and
• a pair of output transmission lines, wherein each one of the pair of output transmission lines is coupled to the drain region of the PMOS transistor and the drain region for the pair of NMOS transistors in each inverter.

An electronic system, comprising:

• a processor;
• a memory device;
• and
• a bus coupling the processor and the memory device, the memory device further including a sense amplifier, comprising:
• a pair of cross-coupled inverters, wherein each inverter includes:
• a p-channel metal oxide semiconductor (PMOS) transistor;
• and
• a pair of n-channel metal oxide semiconductor (NMOS) transistors coupled at a drain region and a source region, and wherein a drain region of the PMOS transistor is coupled to the drain region for the pair of NMOS transistors;
• a complementary pair of bit lines coupling the at least one sense amplifier to a number of memory cells in a memory cell array, and wherein each one of the complementary pair of bit lines couples to a gate of a first one of the pair of NMOS transistors in each inverter;
• and
• a pair of output transmission lines, wherein each one of the pair of output transmission lines is coupled to the drain region of the PMOS transistor and the drain region for the pair of NMOS transistors in each inverter.

An integrated circuit, comprising:

• a processor;
• a memory operatively coupled to the processor;
• and
• wherein the processor and memory are formed on the same semiconductor substrate and the integrated circuit includes at least one sense amplifier, comprising:
• a pair of cross-coupled inverters, wherein each inverter includes:
• a transistor of a first conductivity type;
• a pair of transistors of a second conductivity type coupled at a drain region and coupled at a source region, and wherein the drain region for the pair of transistors is coupled to a drain region of the transistor of the first conductivity type;
• a pair of bit lines, wherein each one of the pair of bit lines is coupled to a gate of a first one of the pair of transistors in each inverter;
• and
• a pair of output transmission lines, wherein each one of the pair of output transmission lines is coupled to the drain region of the pair of transistors and the drain region of the transistor of the first conductivity type in each inverter.

A method for forming a current sense amplifier, comprising:

• cross coupling a pair of inverters, wherein each inverter includes:
• a transistor of a first conductivity type;
• a pair of transistors of a second conductivity type coupled at a drain region and coupled at a source region, and wherein the drain region for the pair of transistors is coupled to a drain region of the transistor of the first conductivity type;
• and
• wherein cross coupling the pair of inverters includes coupling the drain region for the transistor of the first conductivity type and the drain region for the pair of transistors in one inverter to a gate of the transistor of a first conductivity type and to a gate of a first one of the pair of transistors in the other inverter.

A method for forming a sense amplifier, comprising:

• forming and cross coupling a pair of inverters, wherein forming and cross coupling each inverter includes:
• forming a first transistor of a first conductivity type;
• forming a second transistor and a third transistor of a second conductivity type, wherein forming the second and the third transistors includes coupling a drain region and a source region for the second and third transistors, and coupling the drain region for the second and third transistors to a drain region of the first transistor;
• coupling a bit line to a gate of the second transistor in each inverter;
• and
• coupling an output transmission line to the drain region of the first transistor and to the drain region of the second and the third transistors in each inverter.

A method for operating a sense amplifier, comprising:

• equilibrating a first and second bit line, wherein the first bit line is coupled to a gate of a first NMOS transistor in a first inverter in the sense amplifier and the second bit lines is coupled to a gate of a first NMOS transistor in a second inverter in the sense amplifier;
• discharging a memory cell onto the first bit line, wherein discharging a memory cell onto the first bit line drives a signal from a drain region for the first inverter to a gate of a PMOS transistor and to a gate of a second NMOS transistor in the second inverter;
• and
• providing a feedback from a drain region for the second inverter to a gate of a PMOS transistor and a gate of a second NMOS transistor in the first inverter.

A method for operating a sense amplifier, comprising:

• providing a first bit line signal to a gate of a first NMOS transistor coupled at a drain region and a source region to a second NMOS transistor in a first inverter of the sense amplifier;
• providing a second bit line signal to a gate of a first NMOS transistor coupled at a drain region and a source region to a second NMOS transistor in a second inverter of the sense amplifier;
• and
• wherein providing the first and the second bit line signals to the gates of the first and second NMOS transistors isolates the bit line capacitances from a first and second output node on the sense amplifier.