US 2001/0043084 A1 · Semiconductor integrated circuit apparatus

Abstract

There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and a particle noise and noises due to charge redistribution effect or leakage current can be prevented. There is also disclosed a parallel data processing apparatus which features such logic circuitry, the data processing apparatus having both a plurality of data processing units, each having a processor and a memory, and a plurality of hard disks.

Claims21

Dependent claims

A parallel data processing apparatus for processing plural data in parallel by a plurality of processors, wherein:

at least one of said plurality of processors have a plurality of series-connected logic circuits, and
each of said logic circuits has a first logic block consisting of P-type MOS transistors and a second logic block coupled thereto consisting of N-type MOS transistors, and provides an output signal in response to an input signal turning ON transistors of said first logic block.

A parallel data processing apparatus comprising:

a plurality of data processing units each having a processor and a memory;
and
a plurality of hard disks,
wherein each of said data processing units is connected to corresponding ones of said hard disks and said data processing units are in mutual electrical connection to each other via a network, and
wherein each of said processors has a plurality of series-connected logic circuits, and each of said logic circuits has a first logic block consisting of P-type MOS transistors and a second logic block coupled thereto consisting of N-type MOS transistors, and provides an output signal in response to an input signal turning ON transistors of said N-type logic block.

2 more elements

A data processing unit comprising a floating point register unit, a floating point adder unit, a floating point multiplier unit, arithmetic and logic units, an address adder unit, a data cache unit and an instruction cache unit, wherein:

at least one of said floating point register unit, said floating point adder unit, said floating point multiplier unit, said arithmetic and logic units, said address adder unit, said data cache unit and said instruction cache unit have a plurality of series-connected logic circuits, and
each of said logic circuits has a first logic block consisting of P-type MOS transistors and a second logic block consisting of N-type MOS transistors, and provides an output signal in response to an input signal turning ON transistors of said N-type logic block.

Dependencies are inferred from the claim text.

Semiconductor integrated circuit apparatus

Life of this patent

Semiconductor integrated circuit apparatus

Life of this patent

Abstract

Claims21