US 2001/0043082 A1 · Logic/memory circuit having a plurality of operating modes

Abstract

A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.

Claims24

Dependent claims

A logic/memory circuit, comprising:

a logic/memory array having lookup table and product term generator modes, the logic/memory array comprising rows and columns of memory elements associated in pairs within each column, wherein:
when the logic/memory array is in the product term generator mode a pair of memory elements representing a variable stores related values, and when the logic/memory array is in the lookup table mode each memory element stores an independent value, and
each pair of memory elements has an associated product term generating circuit providing a product term based on the values stored in the associated pair of memory elements when the logic/memory array is in the product term generator mode;
a decoder circuit coupled to the logic/memory array and selecting a column of memory elements in the logic/memory array;
and
a multiplexer circuit coupled to the logic/memory array and selecting a row of memory elements in the logic/memory array.

3 more elements

Dependencies are inferred from the claim text.

Logic/memory circuit having a plurality of operating modes

Life of this patent

Logic/memory circuit having a plurality of operating modes

Life of this patent

Abstract

Claims24