Semiconductor package

A semiconductor package comprising:

• a first package substrate having a concave portion;
• a semiconductor chip, fixed within the concave portion, having a major surface and first pads formed on the major surface;
• a second package substrate having (a) opposite first and second major surfaces, (b) a side surface extending between the first and second major surfaces, (c) a first pad forming region adjacent to and along said side surface, (d) second pads formed on the first pad forming region, (e) external electrodes formed on the first major surface of said package substrate, wherein the second major surface of said second package substrate is fixed to the major surface of said semiconductor chip, and wherein the first external electrodes are electrically connected to the second pads;
• a third package substrate stacked into said first package substrate, said third package substrate having (a) an opening defined by an inner surface thereof, (b) opposite first and second major surfaces, (c) third pads formed on a second pad forming region located adjacent to and along the inner surface, and (d) second external electrodes formed on the first major surface of said third package substrate, wherein the second external electrodes are electrically connected to the third pads;
• bonding wires electrically connecting the first pads to the second pads and the third pads;
• and
• a sealing material covering the bonding wires and first and second pads.

A semiconductor package comprising:

• a semiconductor chip having a major surface and first pads formed on the major surface;
• a package substrate including (a) opposite first and second major surfaces, (b) an opening extending between said first and second major surfaces and defined by opposed first and second side surfaces, (c) a pad forming region extending along and proximate said first side surface, (d) second pads formed on said pad forming region, and (e) external electrodes electrically connected to said second pads and formed on the second major surface of said package substrate, wherein the second major surface of said package substrate is fixed to the major surface of said semiconductor chip such that said first pads are aligned within the opening;
• bonding wires electrically connecting the first pads to the second pads;
• and
• a sealing material covering the bonding wires and first and second pads.