Wafer-level package, a method of manufacturing thereof and a method of manufacturing semiconductor devices from such a wafer-level package

A method of manufacturing a wafer-level package comprising the steps of:

• a) preparing a semiconductor wafer having at least one semiconductor chip circuit forming region each provided with a semiconductor chip circuit and a plurality of chip terminals, at least one of said chip terminals being a test chip terminal and at least one being a non-test chip terminal;
• b) providing a redistribution layer including an insulating film having through holes on the semiconductor wafer and an electrically conductive film formed on said insulating film, said film being formed into redistribution traces having a predetermined pattern;
• c) providing external connection terminals and at least one testing member on said redistribution layer, said at least one testing member being provided at an outer region of said at least one semiconductor chip circuit forming region and connected to said test chip terminal via at least one of said redistribution traces;
• and
• d) testing said at least one semiconductor chip circuit using said at least one testing member.

A method of manufacturing a semiconductor device using a wafer-level package comprising the steps of:

• a) manufacturing a wafer-level package including a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;
• at least one external connection terminal electrically connected to said at least one non-test chip terminal;
• at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;
• and
• at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said at least one testing member,
• b) testing said at least one semiconductor chip circuit provided in said at least one semiconductor chip circuit forming region using said at least one testing member;
• and
• c) after said step b), cutting said wafer-level package along said outer region so as to manufacture at least one individualized semiconductor device.

A wafer-level semiconductor device comprising:

• a semiconductor wafer having chip circuit forming regions;
• at least one testing member provided in an outer region of the chip circuit forming regions;
• and
• a line provided on the semiconductor wafer and connecting the at least one testing member and a test terminal provided in one of the chip circuit forming regions.

A semiconductor device comprising:

• a semiconductor chip;
• a test terminal and a non-test terminal provided to the semiconductor chip;
• and
• a line which is connected to the test terminal and extends out of a circuit forming region.