Transistor having a deposited dual-layer spacer structure
AssigneeIntel Corporation
InventorsLAWRENCE N. BRIGHAM, RAYMOND E. COTNER, MAKAREM A. HUSSEIN
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Abstract
A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.
Claims23
A method of forming a transistor, comprising the steps of:
- a. forming a gate electrode over a gate dielectric;
- c. depositing a first dielectric layer over the gate electrode, the first dielectric layer comprising an oxide;
- d. depositing a second dielectric layer over the first dielectric layer;
- and
- e. etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the first dielectric layer, thereby forming a spacer adjacent to the polysilicon gate electrode.
A method of forming a transistor, comprising the steps of:
- a. forming a gate electrode over a gate dielectric, the gate electrode comprising polysilicon;
- b. depositing a first dielectric layer directly on the gate electrode, the first dielectric layer comprising oxide;
- c. depositing a second dielectric layer directly on the first dielectric layer, the second dielectric layer comprising nitride;
- and
- d. etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the first dielectric layer, thereby forming a spacer adjacent to the gate electrode.
A method of forming a transistor, comprising the steps of:
- a. depositing a polysilicon layer over a gate dielectric;
- b. etching the polysilicon layer to form a polysilicon gate electrode;
- c. implanting a first dose of a first material to form a tip region;
- d. depositing a first dielectric layer directly on the polysilicon gate electrode, the first dielectric layer being oxide;
- e. depositing a second dielectric layer directly on the first dielectric layer, the second dielectric layer being nitride;
- f. etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the first dielectric layer, thereby forming a spacer adjacent to the polysilicon gate electrode;
- and
- g. implanting a second dose of a second material to form a source/drain region.
A transistor, comprising:
- a gate dielectric disposed over a semiconductor substrate;
- a gate electrode disposed over the gate dielectric;
- a spacer structure adjacent to the gate electrode, the spacer structure disposed over the semiconductor substrate and comprising a lower deposited material and an upper deposited material, the lower deposited material comprising an oxide;
- a tip region extending laterally beneath the spacer structure within the semiconductor substrate;
- and
- a source/drain region adjacent to the tip region.
Dependencies are inferred from the claim text.