Depletion type MOS semiconductor device and MOS power IC

Abstract

A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p− well region, an n− depletion region formed in the surface layer of the p− well region, to extend from the n+ emitter region to a surface layer of the n− drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT. Other examples of MOS power IC may include circuits suitable for high-speed turn-on or turn-off operations, and circuits for supplying power to an internal control circuit.

Dependencies are inferred from the claim text.