Method for forming a flash memory cell having contoured floating gate surface

A method for forming a floating gate memory cell, the method comprising:

• providing a substrate;
• forming source and drain regions over the substrate;
• depositing an insulating layer over the source and drain regions;
• and
• forming a contoured floating gate positioned over the insulating layer between the source and drain regions, the floating gate being formed by
• forming a floating gate comprising a polysilicon layer over a substrate,
• forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate,
• forming a spacer layer over the oxide layers and the floating gate,
• removing a portion of the spacer layer such that a middle surface of the floating gate positioned laterally toward a middle of the floating gate is expose, and
• removing a portion of the floating gate underlying the exposed middle surface to form the contoured floating gate;
• and
• forming a dielectric layer over the contoured floating gate.

In a floating gate memory cell, a floating gate comprising:

• a first end region adjacent a first lateral end of the floating gate;
• and
• a middle region positioned laterally toward a middle of the floating gate relative to the first end region, the middle region having a vertical thickness which is less than a vertical thickness of the first end region;
• wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first end region and middle region by one or more subsequent fabrication steps.

In a floating gate memory cell, a floating gate comprising:

• a first end region adjacent a first lateral end of the floating gate;
• a second end region adjacent a second lateral end of the floating gate opposite the first lateral end;
• and
• a middle region positioned laterally between the first and second end regions, the middle region having a vertical thickness which is less than a vertical thickness of the first end region and which is less than a vertical thickness of the second end region;
• wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first and second end regions and middle region by one or more subsequent fabrication steps.

A floating gate memory cell comprising:

• a substrate;
• source and drain regions positioned over the substrate;
• an insulating layer positioned over the source and drain regions;
• a floating gate positioned over the insulating layer between the source and drain regions, the floating gate comprising
• a first end region adjacent a first lateral end of the floating gate, and
• a middle region positioned laterally toward a middle of the floating gate relative to the first end region, the middle region having a vertical thickness which is less than a vertical thickness of the first end region,
• wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first end region and middle region by one or more subsequent fabrication steps;
• and
• a control gate positioned over the dielectric insulator.

A floating gate memory cell comprising:

• a substrate;
• source and drain regions positioned over the substrate;
• an insulating layer positioned over the source and drain regions;
• a floating gate positioned over the insulating layer between the source and drain regions, the floating gate comprising
• a first end region adjacent a first lateral end of the floating gate;
• a second end region adjacent a second lateral end of the floating gate opposite the first lateral end, and
• a middle region positioned laterally between the first and second end regions, the middle region having a vertical thickness which is less than a vertical thickness of the first end region and which is less than a vertical thickness of the second end region,
• wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first and second end regions and middle region by one or more subsequent fabrication steps;
• and
• a control gate positioned over the dielectric insulator.