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OwnerKazuaki Kunihiro, Yasuo Ohno +1inventors
InventorsKazuaki Kunihiro, Yasuo Ohno, Yuji Takahashi
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A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contact with the second conductivity layer. Impurity concentration N2 and thickness D of the second conductivity layer are such that the following relationship holds: 1 d > 2 ϵ S φ S eN 2 + 2 ϵ S V bi eN 2 N 1 N 1 + N 2 wherein N1 is the impurity concentration of the first conductivity epitaxial layer, ØS, ∈S and Vbi, are surface potential, dielectric constant and a diffused potential, respectively, of the second conductivity epitaxial layer, and e is an elementary charge of electron. An electrically neutral region is formed in the second conductivity epitaxial layer when no voltage is applied between the gate and the source region, whereby the electrically neutral region functions similarly to the gate of a cascode-connected MOSFET, which improves the breakdown voltage of the FET.
A field effect transistor (FET) comprising a substrate, a first epitaxial layer overlying said substrate and having a first conductivity, a second epitaxial layer formed on said first epitaxial layer and having a second conductivity, source and drain regions in ohmic contact with said second epitaxial layer, and a gate metal formed on said second epitaxial layer in Schottky contact therewith, said second epitaxial layer having an impurity concentration and a thickness such that an electrically neutral region is formed when said gate metal has a potential substantially equal to a potential of said drain region.
A method for fabricating a field effect transistor comprising the steps of depositing a first epitaxial layer having a first conductivity and overlying a substrate, depositing a second epitaxial layer having a second conductivity on said first epitaxial layer, forming an ohmic layer on said second epitaxial layer, forming an ohmic layer having a first conductivity on said second epitaxial layer, forming a gate in Schottky contact with said second epitaxial layer and source and drain regions on said ohmic layer, and selectively etching said second epitaxial layer to form an opening for exposing a portion of said first epitaxial layer by using an etchant, said etchant and a semiconductor material of said epitaxial layer being selected such that an etch rate of said second epitaxial layer is lower than an etch rate of said ohmic layer.
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