Circuit and method for testing an integrated circuit
AssigneeMicron Technology, Inc.
InventorDaniel R. Loughmiller
Life of this patent
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Abstract
A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control signal controls when the integrated circuit (10) is in test mode. The test mode detector (12a) further includes a latch (27) that is responsive to the pulse detector (25) so as to set the latch (27) when the pulse detector (25) detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit (10) in test mode for a period of time that is greater than the duration of the pulse of the control signal.
Claims20
A method for testing an integrated circuit, the method comprising the steps of:
- raising a control signal for the integrated circuit to a voltage that exceeds a threshold level;
- entering test mode in response to the control signal;
- reducing the control signal to a second level that is below the threshold level;
- testing the integrated circuit with test signals for a period of time that exceeds the time that the control signal exceeds the threshold level;
- and
- reducing the control signal to a third, different voltage level so as to exit the test mode.
A test mode detector that places an integrated circuit in test mode, the test mode detector comprising:
- a pulse detector that receives a control signal that indicates when the integrated circuit is in test mode;
- and
- a latch, responsive to the pulse detector, that is set when a pulse of the control signal exceeds a threshold voltage so as to place the integrated circuit in test mode.
A memory device for an electronic system, comprising:
- an array of memory cells;
- an address and control circuit coupled to receive control and address signals from the electronic system for use in accessing the memory cells in the array;
- a test mode detector circuit responsive to a control signal from the electronic system, the test mode detector including:
- a pulse detector that receives a control signal that indicates when the integrated circuit is in test mode;
- and
- a latch, responsive to the pulse detector, that is set when a pulse of the control signal exceeds a threshold voltage so as to place the integrated circuit in test mode.
Dependencies are inferred from the claim text.