Transaction class

A circuit design verification system configured to verify the operation of a design under test, the circuit design verification system comprising:

• a simulation subsystem, wherein said simulation subsystem includes one or more functional models, each of said functional models configured to simulate operation of a corresponding device within said design under test;
• and
• a test subsystem, wherein said test subsystem includes
• a system transaction class containing one or more convenience routines and one or more device transaction pointers,
• a configuration transaction class derived from said system transaction class and containing one or more object references,
• one or more device objects corresponding to said one or more object references, and
• one or more device transaction classes, each of said device transaction classes corresponding to one of said one or more device objects and containing an object reference to said one of said one or more device objects.

A method for testing a circuit design in a verification system, the verification system having a test system, a simulation system and an interface system which couples the test and simulation systems, wherein the method comprises:

• defining a system transaction which contains one or more device transaction pointers and contains one or more convenience routines, wherein said system transaction corresponds to a set of potential simulation system transactions;
• instantiating said one or more devices;
• defining one or more configuration transactions, wherein each of said configuration transactions is derived from said system transaction and contains references to one or more of said devices;
• creating one or more device transactions corresponding to said one or more devices, each of said device transactions having a reference to a corresponding one of said one or more devices;
• and
• executing a test which performs one or more of said configuration transactions.

A computer-readable medium containing a test subsystem of a circuit design verification system, wherein the circuit design verification system includes a simulation subsystem for modeling the operation of a test circuit and an interface subsystem for translating test signals from the test subsystem into simulation signals for the simulation subsystem, wherein the test subsystem on the computer-readable medium comprises:

• a device class;
• one or more device transaction classes, each of which contains a reference to a corresponding device instantiated from said device class;
• a system transaction class which contains one or more device transaction pointers;
• and
• one or more configuration transaction classes which are derived from said system transaction class and inherit one or more methods from said system transaction class, each of said configuration transaction classes containing one or more object references to corresponding ones of said devices;
• wherein said test subsystem is configured to operate on said devices through said device transaction pointers.